Browsing by Author "Lu, Hungwen"

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A 1.5V 7.5uW Programmable Gain Amplifier for Multiple Biomedical Signal Acquisition
(2009)
Kao, Shuo-Ting
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Lu, Hungwen
;
Su, ChauChin
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交大名義發表
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National Chiao Tung University
This paper presents a programmable analog front-end IC for multiple biomedical signal acquisition. By chopper-stabilized technique with an AC feedback circuit, the proposed circuit rejects differential electrode offset, common-mode disturbance and solves the problem of flicker noise. In TSMC 0.18 mu m CMOS process, the proposed circuit occupies an active area of 0.38mm(2). With digital controls, the voltage gain, low-pass and high-pass cutoff frequency could be adjusted in the range of 52db-88db, 0.5Hz-10Hz and 100Hz-400Hz, respectively. With a supply voltage of 1.5V, the proposed circuit achieves an input-referred noise of 90nV*Hz(boolean AND)-0.5, a noise-efficient factor of 6.1 while consuming a total current of 5 mu A.
A Tree-Topology Multiplexer for Multiphase Clock System
(2009-01-01)
Lu, Hungwen
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Su, Chauchin
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Liu, Chien-Nan Jimmy
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電控工程研究所
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Institute of Electrical and Control Engineering
This paper proposes a tree-topology multiplexer (MUX) that employs a multiphase low-frequency clock rather than a high-frequency clock. Analysis and simulation results show g that the proposed design can achieve higher bandwidth and be less ss sensitive to process variations than the conventional single-stage MUX. In order to verify the feasibility, this proposed design is integrated with a multiphase phase-locked loop and a low-voltage differential signaling driver in a 0.18- mu m CMOS technology. Measured results indicate that the proposed design can operate tip to 7 gigabits/s under 0.3-Ul jitter limitation.
Design of an All-Digital LVDS Driver
(2009-08-01)
Lu, Hungwen
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Wang, Hsin-Wen
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Su, Chauchin
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Liu, Chien-Nan Jimmy
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電控工程研究所
This paper presents an all-digital low-voltage-differential-signaling (LVDS) driver design for Serial Advanced Technology Attachment II. A simultaneous-switching-noise reduction technique and an autocalibration mechanism are implemented to suppress switching noise and to handle process and environmental variations. The circuit is implemented in a 0.18-mu m 1P6M CMOS process with a core area of 0.072 mm(2). At 3 Gbps, it consumes 9 mW of power under a 1.8-V power supply or 3 pJ/bit.