Browsing by Author "Lu, Ming-Ching"

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Performance constraints aware voltage islands generation in SoC floorplan design
(2006)
Lu, Ming-Ching
;
Wu, Meng-Chen
;
Chen, Hung-Ming
;
Jiang, Hui-Ru
;
電子工程學系及電子研究所
Using voltage island methodology to reduce power consumption for System-on-a-Chip SoQ designs has ecome more and more popular rec. Currently this approach has been considered either in system-level architecture or post-placement stage. Since hierarchical design and reusable intellectual property (IEP) are widely used, it is necessary to optimize floorplanning/placement methodolo considering voltage islands generation to solve power anFcritical path delay problems. In this paper, we propose a floorplanning methodology considering voltage islands generation and performance constraints. Our method is flexible and can be extended to hierarchical design. The experimental results on some MCNC benchmarks show that our method is effective in meeting performance constraints and simultaneously considers the tradeoff between power routing cost and the assignment of supply voltage in mosules.
Performance-Constrained Voltage Assignment in Multiple Supply Voltage SoC Floorplanning
(2009-12-01)
Wu, Meng-Chen
;
Lu, Ming-Ching
;
Chen, Hung-Ming
;
Jou, Jing-Yang
;
電子工程學系及電子研究所
Using voltage island methodology to reduce power consumption for System-on-a-Chip (SoC) designs has become more and more popular recently. Currently this approach has been considered either in system-level architecture or postplacement stage. Since hierarchical design and reusable intellectual property (IP) are widely used, it is necessary to optimize floorplanning/placement methodology considering voltage islands generation to solve power and critical path delay problems. In this article, we propose a floorplanning methodology considering voltage islands generation and performance constraints. Our method is flexible and can be extended to hierarchical design. The experimental results on some MCNC benchmarks show that our method is effective in meeting performance constraints and can simultaneously consider the tradeoff between power routing cost and total power dissipation.