Browsing by Author "Lu, Ting-Chou"

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A 70nW, 0.3V Temperature Compensation Voltage Reference Consisting of Subthreshold MOSFETs in 65nm CMOS Technology
(2016)
Lu, Ting-Chou
;
Ker, Ming-Dou
;
Zan, Hsiao-Wen
;
電子工程學系及電子研究所
;
光電工程學系
Being operated with 0.3V supply voltage in a standard 65nm CMOS process, a new CMOS temperature compensated voltage reference circuit is proposed with subthreshold transistors and native nMOS. The reference drain current provided by the gate voltage of a subthreshold nMOS output transistor is nearly independent of temperature due to the existence of mutual compensation of mobility and threshold voltage variation. The new proposed temperature compensated voltage reference circuit functions well with the output voltage VREF of 168 mV at room temperature as no extra laser trimming is needed after fabrication. The total power consumption is about 70nW. With the VDD power supply of 0.3V, the temperature coefficient (TC) of voltage reference circuit is 105 ppm/degrees C as temperature varies from -20 degrees C to 100 degrees C. The chip size of the fabricated bandgap reference circuit is 0.0053mm(2).
A 8 Phases 192 MHz Crystal-Less Clock Generator with PVT Calibration
(2017-01)
Lu, Ting-Chou
;
Ker, Ming-Dou
;
Zan, Hsiao-Wen
;
Liu, Jen-Chieh
;
Lee, Yu
A multi-phase crystal-less clock generator (MPCLCG) with a process-voltage-temperature (PVT) calibration circuit is proposed. It operates at 192 MHz with 8 phases outputs, and is implemented as a 0.18pm CMOS process for digital power management systems. A temperature calibrated circuit is proposed to align operational frequency under process and supply voltage variations. It occupies an area of 65 mu m x 75 mu m and consumes 1.1 mW with the power supply of 1.8 V. Temperature coefficient (TC) is 69.5 ppm/degrees C from 0 to 100 degrees C, and 2-point calibration is applied to calibrate PVT variation. The measured period jitter is a 4.58-ps RMS jitter and a 34.55-ps peak-to-peak jitter (P2P jitter) at 192 MHz within 12.67k-hits. At 192 MHz, it shows a 1-MHz-offset phase noise of -102 dBc/Hz. Phase to phase errors and duty cycle errors are less than 5.5% and 4.3%, respectively.
A 8 Phases 192 MHz Crystal-Less Clock Generator with PVT Calibration
(2017-01)
Lu, Ting-Chou
;
Ker, Ming-Dou
;
Zan, Hsiao-Wen
;
Liu, Jen-Chieh
;
Lee, Yu
A multi-phase crystal-less clock generator (MPCLCG) with a process-voltage-temperature (PVT) calibration circuit is proposed. It operates at 192 MHz with 8 phases outputs, and is implemented as a 0.18pm CMOS process for digital power management systems. A temperature calibrated circuit is proposed to align operational frequency under process and supply voltage variations. It occupies an area of 65 mu m x 75 mu m and consumes 1.1 mW with the power supply of 1.8 V. Temperature coefficient (TC) is 69.5 ppm/degrees C from 0 to 100 degrees C, and 2-point calibration is applied to calibrate PVT variation. The measured period jitter is a 4.58-ps RMS jitter and a 34.55-ps peak-to-peak jitter (P2P jitter) at 192 MHz within 12.67k-hits. At 192 MHz, it shows a 1-MHz-offset phase noise of -102 dBc/Hz. Phase to phase errors and duty cycle errors are less than 5.5% and 4.3%, respectively.
An Ultra-Low Voltage CMOS Voltage Controlled Oscillator with Process and Temperature Compensation
(2017-08-01)
Lu, Ting-Chou
;
Ker, Ming-Dou
;
Zan, Hsiao-Wen
;
電子工程學系及電子研究所
;
光電工程學系
Process and temperature variations have become a serious concern for ultra-low voltage (ULV) technology. The clock generator is the essential component for the ULV very-large-scale integration (VLSI). MOSFETs that are operated in the sub-threshold region are widely applied for ULV technology. However, MOSFETs at subthreshold region have relatively high variations with process and temperature. In this paper, process and temperature variations on the clock generators have been studied. This paper presents an ultra-low voltage 2.4GHz CMOS voltage controlled oscillator with temperature and process compensation. A new all-digital auto compensated mechanism to reduce process and temperature variation without any laser trimming is proposed. With the compensated circuit, the VCO frequency-drift is 16.6 times the improvements of the uncompensated one as temperature changes. Furthermore, it also provides low jitter performance.
Design of Bandgap Voltage Reference Circuit with all TFT Devices on Glass Substrate in a 3-mu m UPS Process
(2008)
Lu, Ting-Chou
;
Ker, Ming-Dou
;
Zan, Hsiao-Wen
;
Kuo, Chung-Hung
;
Li, Chun-Huai
A bandgap voltage reference (BGR) circuit designed with the low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) on glass substrate is proposed, which has been successfully verified in a 3-mu m LTPS process. The experimental results have shown that the measured temperature coefficient of the new proposed bandgap voltage reference circuit is around 195 ppm/degrees C under the supply voltage of 10V. The proposed bandgap voltage reference circuit can be applied on precise analog circuits for System-on-Panel (SoP) or System-on-Glass (SoG) applications.
Investigating electron depletion effect in amorphous indium-gallium-zinc-oxide thin-film transistor with a floating capping metal by technology computer-aided design simulation and leakage reduction
(2014-06-01)
Lu, Ting-Chou
;
Chen, Wei-Tsung
;
Zan, Hsiao-Wen
;
Ker, Ming-Dou
;
電機學院
The electron distribution in an amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) with a floating metal-semiconductor (MS) back interface is analyzed using a technology computer-aided design (TCAD) model. The channel geometry (i.e., length and thickness) effect is carefully investigated. At a high work function (i.e., 5 eV) of the capping metal, electrons inside a-IGZO are mostly removed by the capping metal (electron depletion effect). The depletion of the IGZO film leads to an increase in threshold voltage in a-IGZO TFT. TCAD simulation reveals that increasing channel length and decreasing IGZO thickness significantly enhance such an electron depletion effect. Finally, the electron depletion effect is applied to a-IGZO TFT with a high-conductivity IGZO film to greatly suppress the leakage current by over 5 orders. (C) 2014 The Japan Society of Applied Physics
Invited: Wireless sensor nodes for environmental monitoring in Internet of Things
(2016)
Lu, Ting-Chou
;
Huang, Li-Ren
;
Lee, Yu
;
Tsai, Kun-Ju
;
Liao, Yu-Te
This paper presents a self-sustainable landslide surveillance system that detects hazardous water content level in soils and provides real-time landslide warnings to residents, without requiring wired electricity transmission. A self-powered soil water content sensor was applied as the trigger of alert event. It solves the energy supply problem by an environmental interrupt mechanism, which wakes up the sensor and communication circuits in a sensing node only when the water content in monitored soils exceeds a certain threshold, and thus completely eliminates the need for an ALS node to periodically wake up, sense and communicate. By tightly integrating energy harvesting, environment sensing and circuit wake-up, it may well be the most energy-efficient landslide surveillance system designed to monitor water content in soils in the world.
Invited: Wireless sensor nodes for environmental monitoring in Internet of Things
(2016)
Lu, Ting-Chou
;
Huang, Li-Ren
;
Lee, Yu
;
Tsai, Kun-Ju
;
Liao, Yu-Te
This paper presents a self-sustainable landslide surveillance system that detects hazardous water content level in soils and provides real-time landslide warnings to residents, without requiring wired electricity transmission. A self-powered soil water content sensor was applied as the trigger of alert event. It solves the energy supply problem by an environmental interrupt mechanism, which wakes up the sensor and communication circuits in a sensing node only when the water content in monitored soils exceeds a certain threshold, and thus completely eliminates the need for an ALS node to periodically wake up, sense and communicate. By tightly integrating energy harvesting, environment sensing and circuit wake-up, it may well be the most energy-efficient landslide surveillance system designed to monitor water content in soils in the world.
Temperature coefficient of diode-connected LTPS poly-Si TFTs and its application on the bandgap reference circuit
(2008)
Lu, Ting-Chou
;
Zan, Hsiao-Wen
;
Ker, Ming-Dou
;
Huang, Wei-Ming
;
Lin, Kun-Chih
The temperature coefficient (TC) of n-type diode-connected polycrystalline silicon thin-film transistors (poly-Si TFTs) is investigated. The relationship between TC and the activation energy is observed and explained. It is also found that TC is not sensitive to the deviation of the laser crystallization energy. On the contrary, channel width can effectively modulate TC. By using the diode-connected poly-Si TFTs with different channel widths, a new bandgap reference circuit for precise analog circuit design on glass substrate is proposed and realized. From the experimental results in a LTPS process, the output voltage reference exhibits a very low TC of 195 ppm/degrees C, between 25 degrees C and 125 degrees C.
Temperature Coefficient of Poly-Silicon TFT and Its Application on Voltage Reference Circuit With Temperature Compensation in LTPS Process
(2008-10-01)
Lu, Ting-Chou
;
Zan, Hsiao-Wen
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
顯示科技研究所
The temperature coefficient (TC) of n-type polycrystalline silicon thin-film transistors (poly-Si TFTs) is investigated in this paper. The relationship between the TC and the activation energy is observed and explained. From the experimental results, it is also found that TC is not sensitive to the deviation of the laser crystallization energy. On the contrary, channel width can effectively modulate the TC of TFTs. By using the diode-connected poly-Si TFTs with different channel widths, the first voltage reference circuit with temperature compensation for precise analog circuit design on glass substrate is proposed and realized. From the experimental results in a low-temperature poly-Si process, the output voltage of voltage reference circuit with temperature compensation exhibits a very low TC of 195 ppm/C, between 25 degrees C and 125 degrees C. The proposed voltage reference circuit with temperature compensation can be applied to design precise analog circuits for system-on-panel or system-on-glass applications, which enables the analog circuits to be integrated in the active-matrix liquid crystal display panels.