Browsing by Author "Lu, WP"
Now showing 1 - 3 of 3
- Results Per Page
- Sort Options
Item type:Item, An endurance evaluation method for flash EEPROM(2004-05-01) ;Zous, NK ;Chen, YJ ;Chin, CY ;Tsai, WJLu, TCTrap generation is hard to estimate in a Flash cell due to a dynamic stress field during program and erase. In this paper, a linear correlation is found between the erase state V-T rollup, and cycling V-T window. With the knowledge of the time dependence of erase stress field based on Fowler-Nordheim (FN) tunneling, the V-T rollup during cycling is evaluated by incorporating field dependent oxide trap generation. The extracted Delta V-T degradation slope during constant FN stress can be applied quantitatively to predict the V-T window closure during Flash cell cycling.Item type:Item, Characterization of programmed charge lateral distribution in a two-bit storage nitride flash memory cell by using a charge-pumping technique(2006-01-01) ;Gu, SH ;Wang, TH ;Lu, WP ;Ting, WCKu, YHJIn this paper, we use a modified charge pumping technique to characterize the programmed charge lateral distribution in a hot electron program/hot hole erase, two-bit storage nitride Flash memory cell. The stored charge distribution of each bit over the source/drain junctions can be profiled separately. Our result shows that the second programmed bit has a broader stored charge distribution than the first programmed bit. The reason is that a large channel field exists under the first programmed bit during the second bit programming. Such a large field accelerates channel electrons and causes earlier electron injection into the nitride. In addition, we find that programmed charges spread further into the channel as program/erase cycle number increases.Item type:Item, Lateral migration of trapped holes in a nitride storage flash memory cell and its qualification methodology(2004-09-01) ;Zous, NK ;Lee, MY ;Tsai, WJ ;Kuo, AHuang, LTThe negative threshold voltage (V-t) shift of a nitride storage flash memory cell in the erase state will result in an increase in leakage current. By utilizing a charge pumping method, we found that trapped hole lateral migration is responsible for this V-t shift. Hole transport in nitride is characterized by monitoring gate induced drain leakage current and using a thermionic emission model. The hole emission induced V-t shift shows a linear correlation with bake time in a semi-logarithm plot and its slope depends on the bake temperature. Based on the result, an accelerated qualification method for the negative V-t drift is proposed.