Browsing by Author "Lu, Yi-Hsien"

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Electrical properties of low-temperature-compatible p-channel polycrystalline-silicon TFTs using high-kappa gate dielectrics
(2008-04-01)
Yang, Ming-Jui
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Chien, Chao-Hsin
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Lu, Yi-Hsien
;
Shen, Chih-Yen
;
Huang, Tiao-Yuan
In this paper, we describe a systematic study of the electrical properties of low-temperature-compatible p-channel polycrystalline-silicon thin-film transistors (poly-Si TFTs) using HfO2 and HfSiOx high-kappa gate dielectrics. Because of their larger gate capacitance density, the TFTs containing the high-kappa gate dielectrics exhibited superior device performance in terms of higher I-on/I-off current ratios, lower subthreshold swings (SSs), and lower threshold voltages (V-th), relative to conventional deposited-SiO2, albeit with slightly higher OFF-state currents. The TFTs incorporating HfSiOx as the gate dielectric had ca. 1.73 times the mobility (mu(FE)) relative to that of the deposited-SiO2 TFTs; in contrast, the HfO2 TFTs exhibited inferior mobility. We investigated the mechanism for the mobility degradation in these HfO2 TFTs. The immunity of the HfSiOx TFTs was better than that of the HfO2 TFTs-in terms of their V-th shift, SS degradation, mu(FE) degradation, and drive current deterioration-against negative bias temperature instability stressing. Thus, we believe that HfSiOx, rather than HfO2, is a potential candidate for use as a gate-dielectric material in future high-performance poly-Si TFTs.
High-performance and low-temperature-compatible p-channel polycrystalline-silicon TFTs using hafnium-silicate gate dielectric
(2007-10-01)
Yang, Ming-Jui
;
Chien, Chao-Hsin
;
Lu, Yi-Hsien
;
Luo, Guang-Li
;
Chiu, Su-Ching
In this letter, high-performance p-channel polycrystalline-silicon thin-film transistors (TFTs) using hafnium-silicate (HfSiOx) gate dielectric are demonstrated with low-temperature processing. Because of the higher gate-capacitance density, TFTs with HfSiOx. gate dielectric exhibit excellent device performance in terms of higher I-ON/I-OFF current ratio, lower subthreshold swing, and lower threshold voltage (V-th) albeit with slightly higher OFF-state current. More importantly, the mobility of TFTs with HfSiOx gate dielectric is 1.7 times that of TFTs with conventional deposited-SiO2 gate dielectric.
High-Performance GAA Sidewall-Damascened Sub-10-nm In Situ n(+)-Doped Poly-Si NWs Channels Junctionless FETs
(2014-11-01)
Kuo, Po-Yi
;
Lu, Yi-Hsien
;
Chao, Tien-Sheng
;
電子物理學系
;
Department of Electrophysics
The gate-all-around sidewall-damascened sub-10- nm in situ n(+)-doped poly-Si nanowires channels junctionless FETs (GAA SWDNW-JLFETs) with one NW of sub-50-nm(2) cross-sectional area have been successfully fabricated and demonstrated in the category of poly-Si NWs JL transistors for the first time. Some key properties are explored: 1) novel SWDNW processes; 2) dependence of threshold voltage (V-TH) and subthreshold swing (S.S.) on dimension of in situ n(+)-doped poly-Si NWs in GAA SWDNW-JLFETs; and 3) thermal stability of main electrical characteristics under high operating temperature. The high-performance GAA SWDNW-JLFETs show good electrical characteristics: 1) steep S.S. similar to 75 mV/decade; 2) low gate supply voltage (V-G) = 1.5 V; 3) high ON/OFF currents ratio (I-ON/I-OFF) similar to 8 x 10(7) and significantly highthermal stability without implantation processes and hydrogenrelated plasma treatments for future 3-D integrated circuits, system-on-panel, and system-on-chip applications.
High-Performance Poly-Si TFTs of Top-Gate with High-kappa Metal-Gate Combine the Laser Annealed Channel and Glass Substrate
(2011)
Lu, Yi-Hsien
;
Chien, Chao-Hsin
;
Kuo, Po-Yi
;
Yang, Ming-Jui
;
Lin, Hsiao-Yi
We demonstrate high-performance low-temperature poly-Si thin film transistors (LTPS-TFTs) with a TaN/Hf-based top-gate-stack and combine the channel film by laser annealing and glass substrate (glass substrate high-kappa metal-gate thin film transistor, called GSHM-TFTs). The GSHM-TFTs of n-channel (called GSHM-NTFTs) exhibit a very low threshold voltage, low supply voltage (similar to 2 V), steep subthreshold swing (S.S.) similar to 95 mV/dec, and high I(ON)/I(OFF) ratio >10(7). In contrast, GSHM-TFTs of p-channel (called GSHM-PTFTs) exhibit an S.S. similar to 154 mV/dec and an I(ON)/I(OFF) ratio even higher than 10(8). Furthermore, the driving currents are also enhanced in GSHM-TFTs. These significant improvements are due to the combination of laser annealed channel film and the very high gate-capacitance density provided by HfO(2) gate dielectrics with the effective oxide thickness of 14 nm. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3504147] All rights reserved.
High-Performance Poly-Si Thin-Film Transistors With L-Fin Channels
(2012-02-01)
Lu, Yi-Hsien
;
Kuo, Po-Yi
;
Lin, Je-Wei
;
Wu, Yi-Hong
;
Chen, Yi-Hsuan
For the first time, we construct poly-Si thin-film transistors (TFTs) with novel L-shaped poly-Si fin channels (poly-Si TFTs with L-fin channels, called LFin-TFTs). The L-fin channels of LFin-TFTs are similar to the multiple-gated fin channels of FinFETs. The LFin-TFTs exhibit a low supply gate voltage (3 V), a good subthreshold swing (SS) similar to 190 mV/dec, and a high on/off current ratio (I-ON/I-OFF) > 10(6) (V-D = 1 V) without hydrogen-related plasma treatments. After Ni salicidation, the devices exhibit steep SS similar to 148 mV/dec and I-ON/I-OFF similar to 10(7). After NH3 plasma treatment, the characteristics of the devices are further improved. The LFin-TFTs have steeper SS similar to 132 mV/dec, higher I-ON/I-OFF > 10(7), and threshold voltage (V-TH) similar to 0.036 V.
Novel Sub-10-nm Gate-All-Around Si Nanowire Channel Poly-Si TFTs With Raised Source/Drain
(2011-02-01)
Lu, Yi-Hsien
;
Kuo, Po-Yi
;
Wu, Yi-Hong
;
Chen, Yi-Hsuan
;
Chao, Tien-Sheng
We have successfully fabricated novel sub-10-nm gate-all-around Si nanowire (NW) poly-Si TFTs with raised source/drain structure (GAA RSDNW-TFTs). The Si NW dimension is about 7 x 12 nm. A superior smooth elliptical shape is obtained, for the first time, in the category of poly-Si NW TFTs through the use of a novel fabrication process requiring no advanced lithographic tools. The GAA RSDNW-TFTs exhibit low supply gate voltage (3 V), steep subthreshold swing similar to 99 mV/dec, and high I(ON)/I(OFF) > 10(7) (V(D) = 1 V) without hydrogen-related plasma treatments. Furthermore, the DIBL of GAA RSDNW-TFTs is well controlled. These improvements can be attributed to the 3-D gate controllability, raised S/D structure, and sub-10-nm Si NW channel. These novel GAA RSDNW-TFTs are, thus, quite suitable for system-on-panel and 3-D IC applications.
Novel Symmetric Vertical-Channel Ni-Salicided Poly-Si Thin-Film Transistors With High ON/OFF-Current Ratio
(2010-11-01)
Wu, Yi-Hong
;
Kuo, Po-Yi
;
Lu, Yi-Hsien
;
Chen, Yi-Hsuan
;
Chao, Tien-Sheng
We have successfully fabricated the symmetric vertical-channel Ni-salicided polycrystalline silicon thin-film transistors (VSA-TFTs) for the first time. The transfer characteristics of VSA-TFTs show a sharp turning between subthreshold and ON state. The OFF-state currents can be improved by a modified overetching of oxide, equivalent dual-gate structure, and n(+) floating-region length. The ON-state currents can be enhanced by Ni-salicidation. The VSA-TFTs display a good subthreshold swing of 220 mV/dec, steep mobility increase (field-effect mobility of 76 cm(2)/ V . s), and large ON/OFF-current ratio of more than 109 (I(OFF) = 4 x 10 (14), I(ON) = 7 x 10 (5), and W(mask)/L(mask) = 10 mu m/3 mu m).
Reliability Analysis of Symmetric Vertical-Channel Nickel-Salicided Poly-Si Thin-Film Transistors
(2012-08-01)
Wu, Yi-Hong
;
Lin, Je-Wei
;
Lu, Yi-Hsien
;
Kuo, Rou-Han
;
Yen, Li-Chen
"In this paper, a reliability analysis of symmetric Vertical-channel Ni-SAlicided poly-Si thin-film transistors (VSA-TFTs) is performed for the first time. First, we compare the drain-induced barrier-lowering effect (DIBL) of VSA-TFTs. The VSA-TFTs with thinner gate oxide thickness, an offset structure, and a longer floating n(+) region have better immunity to DIBL. Second, VSA-TFTs with a longer floating n(+) region also have better immunity under hot-carrier (HC) stress and self-heating (SH) stress. However, VSA-TFTs with a shorter floating n(+) region also have better immunity to positive gate bias (PGB) stress. Consequently, in order to optimize reliability characteristics, including SH stress, HC stress, and PGB stress, it is necessary to modulate the length of the floating n(+) region. Third, the PGB stress, rather than SH stress or HC stress, becomes a major issue for VSA-TFTs under the stress bias below 4 V. In other words, PGB stress will dominate the degradation behaviors when the stress bias is not high enough to achieve SH stress and HC stress. Finally, the worst degradation condition of VSA-TFTs under HC stress, similar to that of most TFT devices, occurs when the stress of V-G is less than half of V-D"
Symmetric Vertical-Channel Nickel-Salicided Poly-Si Thin-Film Transistors With Self-Aligned Oxide Overetching Structures
(2011-07-01)
Wu, Yi-Hong
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Kuo, Po-Yi
;
Lu, Yi-Hsien
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Chen, Yi-Hsuan
;
Chiang, Tsung-Yu
This paper reports the impacts of NH(3) plasma treatment time, oxide overetching depth, and gate oxide thickness on symmetric vertical-channel Ni-salicided poly-Si thin-film transistors (VSA-TFTs) for the first time. OFF-state currents may be improved by increasing the oxide overetching depth. The ON/OFF current ratio may be also improved by increasing the oxide overetching depth. The NH(3) plasma optimum treatment time of VSA-TFTs is significantly shorter than that of conventional top-gate horizontal-channel TFTs. The performance of VSA-TFTs is degraded by NH(3) plasma treatment for too long a time. VSA-TFTs with 15-nm gate oxide thickness display better subthreshold swing (< 150 mV/dec) than VSA-TFTs with 30-nm gate oxide thickness. OFF-state currents can be improved by increasing L(mask), even when the oxide overetching depth and the gate oxide thickness are changed.