Browsing by Author "Luc, Quang Ho"

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AlGaN/GaN HEMTs With Damage-Free Neutral Beam Etched Gate Recess for High-Performance Millimeter-Wave Applications
(2016-11)
Lin, Yen-Ku
;
Noda, Shuichi
;
Lo, Hsiao-Chieh
;
Liu, Shih-Chien
;
Wu, Chia-Hsun
The electrical performances of gate-recessed AlGaN/GaN high-electron mobility transistors (HEMTs) fabricated using the damage-free neutral beam etching (NBE) method are demonstrated. The NBE method could eliminate the plasma-induced defects generated by irradiating ultraviolet/VUV photons in the conventional inductively coupled plasma reactive ion etching method. The AlGaN/GaN HEMT device fabricated using the new gate recess process exhibited superior electrical performances, including a maximum drain current density (I-DS,I-max) of 1.54 A/mm, low 1/f noise, a current-gain cutoff frequency (f(T)) of 153 GHz, a maximum frequency of oscillation (f(MAX)) of 167 GHz, and a minimum noise figure (NFmin) of 3.28 dB with an associated gain (G(AS)) of 5.06 dB at 54 GHz. Such superior characteristics confirm the inherent advantages of adopting the damage-free NBE process in fabricating GaN devices for millimeter-wave applications.
AlGaN/GaN HEMTs With Damage-Free Neutral Beam Etched Gate Recess for High-Performance Millimeter-Wave Applications (vol 37, pg 1395, 2016)
(2017-01)
Lin, Yen-Ku
;
Noda, Shuichi
;
Lo, Hsiao-Chieh
;
Liu, Shih-Chien
;
Wu, Chia-Hsun
AlGaN/GaN HEMTs With Damage-Free Neutral Beam Etched Gate Recess for High-Performance Millimeter-Wave Applications (vol 37, pg 1395, 2016)
(2017-01)
Lin, Yen-Ku
;
Noda, Shuichi
;
Lo, Hsiao-Chieh
;
Liu, Shih-Chien
;
Wu, Chia-Hsun
AlGaN/GaN MIS-HEMTs With High Quality ALD-Al2O3 Gate Dielectric Using Water and Remote Oxygen Plasma As Oxidants
(2018-12-01)
Wang, Huan-Chung
;
Hsieh, Ting-En
;
Lin, Yueh-Chin
;
Luc, Quang Ho
;
Liu, Shih-Chien
We demonstrate the electrical performances of AlGaN/GaN metal-insulator-semiconductor-high electron mobility transistors (MIS-HEMTs) with high quality Al2O3 gate dielectric deposited by plasma enhanced atomic layer deposition using both H2O and remote O-2 plasma as oxygen sources. Excellent gate-dielectric/GaN interface and Al2O3 film quality were obtained, resulting in a very small threshold voltage hysteresis and a low interface trap density. The MIS-HEMT device exhibited high on/off current ratio of similar to 10(10), steep subthreshold slope, small gate leakage current, low dynamic on-resistance degradation, and effectively current collapse suppression. These results indicate that incorporating remote O-2 plasma in the ALD-Al2O3 deposition process is an effective and simple way to provide high quality gate dielectric for the GaN MIS-HEMTs production.
Evaluation of AlGaN/GaN metal-oxide-semicondutor high-electron mobility transistors with plasma-enhanced atomic layer deposition HfO2/AlN date dielectric for RF power applications
(2017-09-01)
Chiu, Yu Sheng
;
Luc, Quang Ho
;
Lin, Yueh Chin
;
Huang, Jui Chien
;
Dee, Chang Fu
A plasma enhanced atomic layer deposition (PEALD) HfO2/AlN dielectric stack was used as the gate dielectric for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) for high-frequency power device applications. The capacitance-voltage (C-V) curves of the HfO2/AlN/GaN MOS capacitor (MOSCAP) showed a small frequency dispersion along with a very small hysteresis (similar to 50 mV). Moreover, the interface trap density (D-it) was calculated to be 2.7 x 10(11)cm(-1)V(-1) s(-1) at 150 degrees C. Using PEALD-AlN as the interfacial passivation layer (IPL), the drain current of the HfO2/AlN MOS-HEMTs increased by about 46% and the gate leakage current decreased by six orders of magnitude as compared with those of the conventional Schottky gate AlGaN/GaN HEMTs processed using the same epitaxial wafer. The 0.3-mu m-gate-length HfO2/AlN/AlGaN/GaN MOS-HEMTs demonstrated a 2.88W/mm output power, a 23 dB power gain, a 30.2% power-added efficiency at 2.4 GHz, and an improved device linearity as compared with the conventional AlGaN/GaN HEMTs. The third-order intercept point at the output (OIP3) of the MOS-HEMTs was 28.4 as compared with that of 26.5 for the conventional GaN HEMTs. Overall, the MOS-HEMTs with a HfO2/AlN gate stack showed good potential for high-linearity RF power device applications. (C) 2017 The Japan Society of Applied Physics
Growth of high-quality In0.28Ga0.72Sb/AlSb/GaSb/GaAs heterostructure by metalorganic chemical vapor deposition for single-channel Sb-based complementary metal-oxide-semiconductor applications
(2017-07-01)
Huynh, Sa Hoang
;
Ha, Minh Thien Huu
;
Do, Huy Binh
;
Nguyen, Tuan Anh
;
Yu, Hung Wei
The growth of high-quality In0.28Ga0.72Sb epilayer on an AlSb/GaSb/GaAs heterostructure by metalorganic chemical vapor deposition is demonstrated. The In0.28Ga0.72Sb epilayer has a fully relaxed surface roughness of similar to 1.0nm and a low threading dislocation density of similar to 6.2 x 10(6)cm(-2). The valence band offset (VBO) of 3.11 eV and conduction band offset (CBO) of 3.21 eV for an Al2O3/In0.28Ga0.72Sb interface extracted from X-ray photoemission spectroscopy data highlight its suitability for use in single-channel InGaSb-based complementary metal-oxide-semiconductor (CMOS) applications. The type-I straddling gap of an In0.28Ga0.72Sb/AlSb heterojunction with a VBO of 0.47 eV and CBO of 0.65 eV is also sufficient to prevent both electron and hole leakage currents in CMOS devices. (C) 2017 The Japan Society of Applied Physics
High-Performance Normally-OFF GaN MIS-HEMTs Using Hybrid Ferroelectric Charge Trap Gate Stack (FEG-HEMT) for Power Device Applications
(2018-07-01)
Wu, Chia-Hsun
;
Han, Ping-Cheng
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Liu, Shih-Chien
;
Hsieh, Ting-En
;
Lumbantoruan, Franky Juanda
A GaN metal-insulator-semiconductor-high electron mobility transistor (HEMT) using hybrid ferroelectric charge trap gate stack (FEG-HEMT) is demonstrated for normally-OFF operation. The ferroelectric (FE) polarization increases the number of trapped charges in the HfON charge trapping layer, leading to high positive threshold voltage (V-th) shift for the normally-OFF device. Besides, under the positive bias temperature instability (PBTI) test, the internal electric field induced by FE polarization causes smoother slope of the conduction band in FE gate stack, resulting in better V-th stability. With the proposed hybrid FE charge trap gate stack, the device exhibits a high V-th of +2.71 V at I-DS = 1 mu A/mm, a high maximum current density of 820 mA/mm and low on-resistance (R-ON) of 11.1 Omega . mm. The FE device also shows good V-th-temperature stability compared to the non-FE device results. Besides, a high current device with 40 A is also fabricated in this letter to demonstrate the feasibility of the proposed FEG-HEMT device for high power device application.
In0.53Ga0.47As FinFET and GAA-FET With Remote-Plasma Treatment
(2018-03-01)
Luc, Quang Ho
;
Yang, Kun Sheng
;
Lin, Jia Wei
;
Chang, Chia Chi
;
Huy Binh Do
This letter presents a remote NH3/N-2 plasma treatment after gate oxide deposition for improving the electrical characteristics and the reliability of In0.53Ga0.47As FinFET. The plasma treatment enhanced drive current (I-DS), transconductance (G(m)), subthreshold swing (SS), flicker noise, and positive bias temperature lifetime, suggesting that this plasma treatment significantly improves the quality of the etched In0.53Ga0.47As channel interface. In0.53Ga0.47As FinFETs and gate-all-around FETs were fabricated with the proposed in situ remote-plasma treatment and characterized.
Investigation of Multilayer TiNi Alloys as the Gate Metal for nMOS In0.53Ga0.47As
(2016-12)
Do, Huy Binh
;
Luc, Quang Ho
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Ha, Minh Thien Huu
;
Huynh, Sa Hoang
;
Hu, Chenming Calvin
To achieve low power consumption for CMOS devices, the gate metals must have effective work function (EWF) aligned with the band edges of the channel material and have a small WF variation (WFV). The multilayer TiNi alloys have been successfully applied as the gate metals for HfO2/In0.53Ga0.47As MOS devices in this paper. The EWF of TiNi alloys was found to increase from 4.41 eV for as-deposited sample to 4.62 eV after the alloy was annealed due to the diffusion of Ni atoms into Ti layer. The multilayer TiNi alloy remained amorphous phase with small WFV until annealed at 600 degrees C. The TiNi alloy is thermally more stable as compared with either Ti or Ni metal, because the TiOxNi interfacial layer prevents the diffusion of Ni atoms into HfO2 film and the further reaction of Ti with HfO2. The results can be applied for InGaAs nMOS fabrication.
Normally-Off Tri-Gate GaN MIS-HEMTs with 0.76 m Omega center dot cm(2) Specific On-Resistance for Power Device Applications
(2019-08-01)
Wu, Chia-Hsun
;
Chen, Jian-You
;
Han, Ping-Cheng
;
Lee, Ming-Wen
;
Yang, Kun-Sheng
A GaN metal-insulator-semiconductor high electronmobility transistor (MIS-HEMT) using tri-gate architecture and hybrid ferroelectric charge trap gate stack is demonstrated for normally-off operation. Compared with the conventional planar device, the tri-gate device has the 2-D electron gas (2-DEG) channel exposed on the nanowire sidewalls, so that the trapped charges in the HfON charge-trapping layer can easily deplete the channel from the sidewalls, leading to a high positive threshold voltage (V-th) to realize the normally-off operation. Moreover, through this electrostatic control on the sidewall, a high density of negative charge caused by hybrid ferroelectric charge trap gate stack with the optimized tri-gate structure, the tri-gate device can achieve normally-off GaN device with both low on-resistance (R-ON) and high positive V-th. The designed tri-gate device exhibits a high V-th of +2.61 V at current density (I-DS) = 1 mu A/mm, a high maximum current density (I-DS, MAX) of 896 mA/mm, a low R-ON of 5.0 Omega center dot mm and a high breakdown voltage (BV) of 788 V. To the best of our knowledge, the proposed tri-gate device shows the lowest specific on-resistance (R-ON,R- SP) among reported normallyoff GaN device results with BV > 650 V.
Plasma Enhanced Atomic Layer Deposition Passivated HfO2/AlN/In0.53Ga0.47As MOSCAPs With Sub-Nanometer Equivalent Oxide Thickness and Low Interface Trap Density
(2015-12-01)
Luc, Quang Ho
;
Do, Huy Binh
;
Ha, Minh Thien Huu
;
Hu, Chenming Calvin
;
Lin, Yueh Chin
The impact of in situ plasma-enhanced atomic layer deposition passivation on the electrical properties of HfO2/In0.53Ga0.47As metal-oxide-semiconductor capacitors (MOSCAPs) has been studied. Excellent interface quality of high-k/III-V is achieved by aluminum nitride (AlN) interfacial passivation layer, including strong inversion behaviors and unpinned Fermi level. The band alignment of HfO2/AlN/In0.53Ga0.47As structure with the valence band offsets of 2.81 +/- 0.1 eV and the conduction band offsets of 1.9 +/- 0.1 eV was obtained. Better interface and optimized high-k dielectric qualities are achieved using post remote-plasma treatment with either N-2/H-2 or NH3 gases. Sub-nanometer equivalent oxide thickness HfO2/AlN/In0.53Ga0.47As MOSCAPs with low interface trap density and low leakage current density have been characterized.
Study of the interface stability of the metal (Mo, Ni, Pd)/HfO2/AlN/InGaAs MOS devices
(2017-08-01)
Do, Huy Binh
;
Luc, Quang Ho
;
Ha, Minh Thien Huu
;
Huynh, Sa Hoang
;
Nguyen, Tuan Anh
The degeneration of the metal/HfO2\ interfaces for Mo, Ni, and Pd gate metals was studied in this paper. An unstable PdOx interfacial layer formed at the Pd/HfO2 interface, inducing the oxygen segregation for the Pd/HfO2/InGaAs metal oxide capacitor (MOSCAP). The low dissociation energy for the Pd-O bond was the reason for oxygen segregation. The PdOx layer contains O2- and OH- ions which are mobile during thermal annealing and electrical stress test. The phenomenon was not observed for the (Mo,Ni)/HfO2/InGaAs MOSCAPs. The results provide the guidance for choosing the proper metal electrode for the InGaAs based MOSFET. (C) 2017 Author(s).
The effect of a and Ga intermediate layer on the interfacial layer properties of epitaxial GaSb on GaSb grown by metalorganic chemical vapor deposition
(2019-01-01)
Ha, Minh Thien Huu
;
Huynh, Sa Hoang
;
Do, Huy Binh
;
Lee, Ching Ting
;
Luc, Quang Ho
A method for the growth of high quality GaSb epilayer on GaAs (001) substrate is demonstrated in this study. It is found that a superior GaSb/GaAs interface can be obtained by depositing a thin Sb-precursor layer on the GaAs substrate containing a GaAs buffer layer. It is suggested that the growth occurs via the interface misfit (IMF) growth mode. Without this treatment, GaSb epilayer may grow according to the Stranski-Krastanov mechanism or via a blend of the Stranski-Krastanov and IMF mechanisms, leading to an inferior GaSb/GaAs interface. This could be due to the intermixing of anions, leading to the turbulent composition and misfit dislocation distribution at the heterointerface. It appears that with the addition of a Sb layer, IMF arrays can be formed at GaSb/GaAs interface resulting in superior GaSb layer without the need for changing the growth parameters.