Browsing by Author "Ma, Ming-Wen"

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A highly reliable multi-level and 2-bit/cell operation of wrapped-select-gate (WSG) SONOS memory with optimized ONO thickness
(2007)
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Peng, Wu-Chin
;
Yang, Wen-Luh
;
Wang, Jer-Chyi
High-performance wrapped-select-gate (WSG) SONOS (silicon-oxide-nitride-silicon) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism with different ONO thickness in WSG-SONOS memory was well investigated. The different programming efficiency of the WSG-SONOS memory with different ONO thickness can be explained by the lateral electrical field extracted from the simulation. Furthermore, multi-level storage is easily obtained and well V-th distribution is also presented. High program/erase speed (10us/5ms) and low programming current (3.5uA) are performed to achieve the multi-level operation with excellent gate and drain disturbance, second-bit effect, data retention and endurance.
A reliability model for low-temperature polycrystalline silicon thin-film transistors
(2007-05-01)
Chen, Chih-Yang
;
Lee, Jam-Wem
;
Lee, Po-Hao
;
Chen, Wei-Cheng
;
Lin, Hsiao-Yi
We proposed here a reliability model that successfully. introduces both the physical mechanisms of negative bias temperature instability (NBTI) and hot carrier stress (HCS) for p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The proposed model is highly matched with the experimental results, in which the NBTI dominates the device reliability at small negative drain bias while the HCS dominates the degradation at large negative drain bias. In summary, the proposed model provides a comprehensive way to predict the lifetime of the p-channel LTPS TFTs, which is especially necessary for the system-on-panel circuitry design.
Analysis of negative bias temperature instability in body-tied low-temperature polycrystalline silicon thin-film transistors
(2008-02-01)
Chen, Chih-Yang
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Ma, Ming-Wen
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Chen, Wei-Cheng
;
Lin, Hsiao-Yi
;
Yeh, Kuan-Lin
Negative bias temperature instability (NBTI) degradation mechanism in body-tied low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is analyzed by the charge-pumping (CP) technique. The properties of bulk trap states (including interface and grain boundary trap states) are directly characterized from the CP current. The increase of the fixed oxide charges is also extracted, which has not been quantified in previous studies of NBTI degradation in LTPS TFTs. The experimental results confirm that the NBTI degradation in LTPS TFTs is caused by the generation of bulk trap states and oxide trap states.
Bias temperature instabilities for low-temperature polycrystalline silicon complementary thin-film transistors
(2007)
Chen, Chih-Yang
;
Lee, Jam-Wem
;
Ma, Ming-Wen
;
Chen, Wei-Cheng
;
Lin, Hsiao-Yi
The degradation mechanisms of both negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) were studied for low-temperature polycrystalline silicon complementary thin-film transistors. Measurements show that both NBTI and PBTI are highly bias dependent; however, the effect of the temperature is only functional on the NBTI stress. Furthermore, instead of interfacial trap-state generation during the NBTI stress, the PBTI stress passivates the interface trap states. We conclude that the diffusion-controlled electrochemical reactions dominate the NBTI degradation while charge trapping in the gate dielectric controls the PBTI degradation. (c) 2007 The Electrochemical Society.
Characteristics of HfO(2)/Poly-Si Interfacial Layer on CMOS LTPS-TFTs With HfO(2) Gate Dielectric and O(2) Plasma Surface Treatment
(2008-12-01)
Ma, Ming-Wen
;
Chiang, Tsung-Yu
;
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Lei, Tan-Fu
In this paper, high-performance complementary-metal-oxide-semiconductor low-temperature polycrystalline-silicon thin-film transistors (CMOS LTPS-TFTs) with HfO(2) gate dielectric are fabricated on one wafer for the first time. Low threshold voltage and excellent subthreshold swing can be achieved simultaneously for N- and P-channel LTPS-TFTs without hydrogenation. In addition, the impacts of the HfO(2)/poly-Si interfacial layer on N- and P-channel LTPS-TFTs are also specified. In order to enhance the characteristics of HfO(2) LTPS-TFT further, oxygen plasma surface treatment is employed to improve the interface quality and passivate the defects of channel grain boundaries, thus increasing the carrier mobility and reducing the phonon scattering. The CMOS LTPS-TFTs with HfO(2) gate dielectric and oxygen plasma treatment would be suitable for the application of system-on-panel.
Characteristics of PBTI and hot carrier stress for LTPS-TFT with high-kappa gate dielectric
(2008-02-01)
Ma, Ming-Wen
;
Chen, Chih-Yang
;
Su, Chun-Jung
;
Wu, Woei-Cherng
;
Wu, Yi-Hong
In this letter, the characteristics of positive bias temperature instability (PBTI) and hot carrier stress (HCS) for the low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO2 gate dielectric are well investigated for the first time. Under room temperature stress condition, the PBTI shows a more serious degradation than does HCS, indicating that the gate bias stress would dominate the hot carrier degradation behavior for HfO2 LTPS-TFT. In addition, an abnormal behavior of the I-min degradation with different drain bias stress under high-temperature stress condition is also observed and identified in this letter. The degradation of device's performance under high-temperature stress condition can be attributed to the damages of both the HfO2 gate dielectric and the poly-Si grain boundaries.
Dynamic negative bias temperature instability in low-temperature poly-Si thin-film transistors
(2007)
Chen, Chih-Yang
;
Wang, Tong-Yi
;
Ma, Ming-Wen
;
Chen, Wei-Cheng
;
Lin, Hsiao-Yi
Dynamic negative bias temperature instability in p-channel low-temperature poly-Si thin-film transistors was studied in this paper. The degradation of the devices was found to be voltage and temperature dependent. In addition, the frequency and duty ratio of the gate pulse affects the degree of the device degradation. The mechanism of the device degradation was investigated, and a physical model is proposed to explain the mechanism.
Electrical Characteristics of High Performance SPC and MILC p-Channel LTPS-TFT with High-kappa Gate Dielectric
(2009)
Ma, Ming-Wen
;
Chiang, Tsung-Yu
;
Yeh, Chi-Ruei
;
Chao, Tien-Sheng
;
Lei, Tan-Fu
In this article, high performance p-channel, low temperature polysilicon thin-film transistors (LTPS-TFTs) are fabricated by using HfO(2) gate dielectric and two crystallization methods, solid phase crystallization (SPC) and metal-induced lateral crystallization (MILC) are compared. High field-effect mobility mu(FE) 114 and 215 cm(2)/V s), ultralow subthreshold swing (SS similar to 145 and 107 mV/decade), and low threshold voltage (V(th) similar to -1.05 and -0.75 V) are derived from SPC- and MILC-TFTs with HfO(2) gate dielectric, respectively. These excellent electrical characteristics are due to low trap states and much higher gate capacitance density with equivalent oxide thickness similar to 12.3 nm, resulting in lower operation voltage within 2 V of LTPS-TFT without any passivation method. The comparison of SPC and MILC p-channel LTPS-TFTs with HfO(2) gate dielectric is demonstrated. (C) 2009 The Electrochemical Society. [DOI: 10.1149/1.3177277] All rights reserved.
Fluorinated HfO2 Gate Dielectrics Engineering for CMOS by pre- and post-CF4 Plasma Passivation
(2008)
Wu, Woei-Chemg
;
Lai, Chao-Sung
;
Lee, Shih-Ching
;
Ma, Ming-Wen
;
Chao, Tien-Sheng
In this paper, we demonstrate TaN/Fluorinated HfO2 CMOS devices, focusing on symmetry and asymmetry fluorine incorporation at top or bottom HfO2 interfaces. 16% permittivity enhancement, 65% and 91% mobility increases for electron and hole, respectively, under high electric field was achieved. Reliability of n- and p-MOSFET was improved 3 orders and 8% for GIDL and hot carrier immunity, respectively. A physical model of shallow and deep trapping level affected by fluorine was proposed to explain the NBTI and PBTI improvements.
Fringing electric field effect on 65-nm-node fully depleted silicon-on-insulator devices
(2006-09-01)
Ma, Ming-Wen
;
Chao, Tien-Sheng
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Kao, Kuo-Hsing
;
Huang, Jyun-Siang
;
Lei, Tan-Fu
In this study, the fringing electric field effect on 65-nm-node technology fully depleted silicon-on-insulator (FD SOI) device is comprehensively examined. A new anomalous degradation in device on-state/off-state characteristics on a nanoscale metaloxide-semiconductor field-effect transistor (MOSFET) with high-kappa gate dielectrics is reported, the so-called fringing-induced barrier lowering (FIBL). This is due to the decrease in fringing electric field and increase in the gate dielectric thickness when gate dielectric permittivity increased. We observe that FIBL can be effectively suppressed using a stack gate dielectric structure. In addition, we also implement a high-kappa offset spacer to further improve the on-state driving current I-on to approximately 26% higher than that of a conventional silicon dioxide offset spacer and reduce the off-state leakage current I-off by about 34%. This benefit is due to the enhanced high vertical channel electric field obtained via the offset spacer using a high-kappa material as a spacer. This enhanced fringing electric field can markedly increase I-on/I-off current ratio and reduce subthreshold swing (S-factor) to improve MOSFET performance, which implies that gate-to-channel controllability can be improved markedly. This would play an important role beyond the 65-nm-node technology.
High-kappa material sidewall with source/drain-to-gate non-overlapped structure for low standby power applications
(2006-11-01)
Ma, Ming-Wen
;
Chao, Tien-Sheng
;
Kao, Kuo-Hsing
;
Huang, Jyun-Siang
;
Lei, Tan-Fu
In this paper, fully depleted silicon-on-insulator (SOI) devices with source/drain extension shifts and a high-kappa offset spacers were investigated in detail. The calculated results show that the source/drain extension shift can decrease off-state leakage current I-off significantly by utilizing the extra electron barrier height in the source/drain extension shift region to reduce standby power dissipation. However, the on-state driving current In is also sacrificed simultaneously. To overcome this drawback, a high-kappa offset spacer is used to increase the on-state driving current I-on effectively by enhancing the vertical fringing electric field which elevates the channel voltage drop and reduces series resistance.
High-performance metal-induced laterally crystallized polycrystalline silicon p-channel thin-film transistor with TaN/HfO2 gate stack structure
(2008-06-01)
Ma, Ming-Wen
;
Chao, Tien-Sheng
;
Su, Chun-Jung
;
Wu, Woei-Cherng
;
Kao, Kuo-Hsing
In this letter, high-performance low-temperature poly-Si p-channel thin-film transistor with metal-induced lateral-crystallization (MILC) channel layer and TaN/HfO2 gate stack is demonstrated for the first time. The devices of low threshold voltage V-TH similar to 0.095 V, excellent subthreshold swing S.S. similar to 83 mV/dec., and high field-effect mobility mu(FE) similar to 240 cm(2)/V center dot s are achieved without any defect passivation methods. These significant improvements are due to the MILC channel film and the very high gate-capacitance density provided by HfO2 gate dielectric with the effective oxide thickness of 5.12 mn.
High-performance p-channel LTPS-TFT using HfO(2) gate dielectric and nitrogen ion implantation
(2009-07-01)
Ma, Ming-Wen
;
Chiang, Tsung-Yu
;
Chao, Tien-Sheng
;
Lei, Tan-Fu
;
電子物理學系
In this communication, a high-performance p-channel low-temperature poly-Si thin-film transistor with HfO(2) gate dielectric and nitrogen ion implantation is demonstrated for the first time. A low threshold voltage V(TH) = -0.8 V, excellent subthreshold swing S.S. = 0.123 V/decade, high field effect mobility mu(FE) = 64.14 cm(2) V(-1) s(-1) and high driving current I(Dsat) = 9.14 mu A mu m(-1) @ 3 V operation voltage of the p-channel LTPS-TFT can be achieved. The high performance characteristics are attributed to the very low effective oxide thickness EOT = 8.4 nm provided by the HfO(2) gate dielectric and the passivation of effective interface states and grain boundary traps by the nitrogen ion implantation treatment. It would be very suitable for the application of a high-speed and low-power pixel-driving device in flat-panel displays.
High-performance p-channel LTPS-TFT using HfO2 gate dielectric and nitrogen ion implantation
(2009-07-01)
Ma, Ming-Wen
;
Chiang, Tsung-Yu
;
Chao, Tien-Sheng
;
Lei, Tan-Fu
;
電子物理學系
In this communication, a high-performance p-channel low-temperature poly-Si thin-film transistor with HfO2 gate dielectric and nitrogen ion implantation is demonstrated for the first time. A low threshold voltage V-TH = -0.8 V, excellent subthreshold swing S.S. = 0.123 V/decade, high field effect mobility mu(FE) = 64.14 cm(2) V-1 s(-1) and high driving current I-Dsat = 9.14 mu A mu m(-1) @ 3 V operation voltage of the p-channel LTPS-TFT can be achieved. The high performance characteristics are attributed to the very low effective oxide thickness EOT = 8.4 nm provided by the HfO2 gate dielectric and the passivation of effective interface states and grain boundary traps by the nitrogen ion implantation treatment. It would be very suitable for the application of a high-speed and low-power pixel-driving device in flat-panel displays.
Impact of high-k offset spacer in 65-nm node SOI devices
(2007-03-01)
Ma, Ming-Wen
;
Wu, Chien-Hung
;
Yang, Tsung-Yu
;
Kao, Kuo-Hsing
;
Wu, Woei-Cherng
In this letter, 65-nm node silicon-on-insulator devices with high-k, offset spacer dielectric were investigated by extensive 2-D device simulation. The result shows that the high-k, offset spacer dielectric can effectively increase the ON-state driving current I-ON and reduce the OFF leakage current I-OFF due to the high vertical fringing electric field effect. This fringing field can significantly improve the I-ON/I-OFF current ratio and the subthreshold swing compared with the conventional oxide spacer. Consequently, the gate-to-channel control ability is enhanced by the fringing field via the high-k offset spacer dielectric.
Impacts of fluorine ion implantation with low-temperature solid-phase crystallized activation on high-kappa LTPS-TFT
(2008-02-01)
Ma, Ming-Wen
;
Chen, Chih-Yang
;
Su, Chun-Jung
;
Wu, Woei-Cherng
;
Wu, Yi-Hong
In this letter, fluorine ion implantation with low-temperature solid-phase crystallized activation scheme is used to obtain a high-performance HfO2 low-temperature poly-Si thin-film transistor (LTPS-TFT) for the first time. The secondary ion mass spectrometer (SIMS) analysis shows a different fluorine profile compared to that annealed at high temperature. About one order current reduction of I-min is achieved because 25% grain-boundary traps are passivated by fluorine implantation. In addition, the threshold voltage instability of hot carrier stress is also improved with the introduction of fluorine. The LTPS-TFT with HfO2 gate dielectric and fluorine preimplantation can simultaneously achieve low V-TH similar to 1.32 V, excellent subthreshold swing similar to 0.141 V/dec, and high I-ON/I-min current ratio 1.98 x 10(7).
Impacts of N-2 and NH3 Plasma Surface Treatments on High-Performance LTPS-TFT With High-kappa Gate Dielectric
(2008-11-01)
Ma, Ming-Wen
;
Chao, Tien-Sheng
;
Chiang, Tsung-Yu
;
Wu, Woei-Cherng
;
Lei, Tan-Fu
Low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) with high-kappa gate dielectrics and plasma surface treatments are demonstrated for the first time. Significant field-effect mobility mu(FE) improvements of similar to 86.0% and 112.5% are observed for LTPS-TFTs with HfO2 gate dielectric after N-2 and NH3 plasma surface treatments, respectively. In addition, the N2 and NH3 plasma surface treatments can also reduce surface roughness scattering to enhance the field-effect mobility mu(FE) at high gate bias voltage V-G, resulting in 217.0% and 219.6% improvements in driving current, respectively. As a result, high-performance LTPS-TFT with low threshold voltage V-TH similar to 0.33 V, excellent subthreshold swing S.S. similar to 0.156 V/decade, and high field-effect mobility mu(FE) similar to 62.02 cm(2) /V . s would be suitable for the application of system-on-panel.
Impacts of nitric acid oxidation on low-temperature polycrystalline silicon TFTs with high-k gate dielectric
(2007)
Yang, Tsung-Yu
;
Ma, Ming-Wen
;
Kao, Kuo-Hsing
;
Su, Chun-Jung
;
Chao, Tien-Sheng
In this paper, low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFrs) with HfO2 gate dielectric and nitric acid oxidation pre-treatment is investigated. Significant improvement on on/off current ratio and field effect mobility is observed due to the nitric acid oxidation pre-treatment. An excellent on/off current ratio and subthreshold swing, as well as low threshold voltage and I-off can be achieved without any other hydrogen passivation treatments. These improved performances can be attributed to both the high gate capacitance density using high-k gate dielectric and the good interface quality by nitric acid oxidation of poly-silicon.
Improvement on performance and reliability of TaN/HfO2 LTPS-TFTs with fluorine implantation
(2008-03-01)
Ma, Ming-Wen
;
Chen, Chih-Yang
;
Su, Chun-Jung
;
Wu, Woei-Cherng
;
Yang, Tsung-Yu
In this paper, we demonstrate the low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) with TaN metal-gate and HfO2 gate dielectric to achieve high performance characteristics. A high performance LTPS-TFT with low threshold voltage 0.9 V, excellent subthreshold swing 0.15 V/decade and high I-on/I-min current ratio 1.9 x 10(6) are derived without any hydrogen treatment. In addition, we also introduce the fluorine implantation prior to the Si thin-film crystallization to passivate the defects in grain-boundaries of the channel film and HfO2/polysilicon interface. Significant improvements on subthreshold swing and I-min are observed. In addition, the transconductance degradation and threshold voltage instability due to hot carrier stress is also investigated, respectively. Finally, we derive a high reliability and performance LTPS-TFT with low threshold voltage similar to 1.38 V, ultra-low subthreshold swing 0.132 V/decade and high I-on/I-min current ratio 1.21 x 10(7), which is suitable for the application of system-on panel (SOP). (c) 2007 Elsevier Ltd. All rights reserved.
MILC-TFT With High-kappa Dielectrics for One-Time-Programmable Memory Application
(2009-09-01)
Chiang, Tsung-Yu
;
Ma, Ming-Wen
;
Wu, Yi-Hong
;
Kuo, Po-Yi
;
Wang, Kuan-Ti
In this letter, for the first time, one-time-programmable (OTP) memory fabricated on the low-temperature poly-Si p-cbannel thin-film transistor (TFT) with metal-induced lateral-crystallization channel layer and high-kappa dielectrics is demonstrated. The state of this OTP memory can be identified by the scheme of gate-induced drain leakage current measurement. The OTP-TFT memory has good electrical characteristics in terms of low threshold voltage V(th) similar to -0.78 V, excellent subthreshold swing similar to 105 mV/dec, low operation voltage, faster programming speeds, and excellent reliability characteristics.