Browsing by Author "Ma, William Cheng-Yu"

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A Novel p-n-Diode Structure of SONOS-Type TFT NVM With Embedded Silicon Nanocrystals
(2010-11-01)
Chiang, Tsung-Yu
;
Ma, William Cheng-Yu
;
Wu, Yi-Hong
;
Wang, Kuan-Ti
;
Chao, Tien-Sheng
In this letter, for the first time, a novel p-n-diode (PND) structure of SONOS-type thin-film transistor (TFT) nonvolatile memory (NVM) with embedded silicon nanocrystals (Si-NCs) in the silicon nitride layer using an in situ method is successfully demonstrated. This novel structure has many advantages, including high density and suitability for 3-D circuit integration. Hot-electron injection and hot-hole injection are used as the program and erase methods, respectively. The sensing current of the three-terminal PND-TFT NVM is 10(-7) A by the band-to-band tunneling current. A much larger memory window (> 12 V) and good data retention time (> 10(8) s for 12% charge loss) are exhibited. The device appears to have great potential for system-on-panel applications.
A Novel p-n-Diode Structure of SONOS-Type TFT NVM With Embedded Silicon Nanocrystals
(2010-11-01)
Chiang, Tsung-Yu
;
Ma, William Cheng-Yu
;
Wu, Yi-Hong
;
Wang, Kuan-Ti
;
Chao, Tien-Sheng
In this letter, for the first time, a novel p-n-diode (PND) structure of SONOS-type thin-film transistor (TFT) nonvolatile memory (NVM) with embedded silicon nanocrystals (Si-NCs) in the silicon nitride layer using an in situ method is successfully demonstrated. This novel structure has many advantages, including high density and suitability for 3-D circuit integration. Hot-electron injection and hot-hole injection are used as the program and erase methods, respectively. The sensing current of the three-terminal PND-TFT NVM is 10(-7) A by the band-to-band tunneling current. A much larger memory window (> 12 V) and good data retention time (> 10(8) s for 12% charge loss) are exhibited. The device appears to have great potential for system-on-panel applications.
Channel Film Thickness Effect of Low-Temperature Polycrystalline-Silicon Thin-Film Transistors
(2011-04-01)
Ma, William Cheng-Yu
;
Chiang, Tsung-Yu
;
Yeh, Chi-Ruei
;
Chao, Tien-Sheng
;
Lei, Tan-Fu
In this paper, the channel-film-thickness effect of low-temperature polycrystalline-Si thin-film transistors (LTPS-TFTs) is investigated. Greater channel film thickness can provide a higher field-effect mobility mu FE, rising from 14.33 to 22.33 cm(2)/V . s, as the channel film thickness increases from 55 to 120 nm, due to grain-size effect. In addition, varying the channel film thickness of LTPS-TFTs results in different junction leakage current due to the source/drain (S/D) junction area effect. Moreover, the S/D series resistance also significantly increases when the channel film thickness is reduced from 120 to 35 nm, leading to poor field-effect mobility mu FE and driving current. Consequently, the optimum channel film thickness for active-matrix liquid-crystal displays may be identified.
Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon Nanocrystals
(2010-08-01)
Chiang, Tsung-Yu
;
Wu, Yi-Hong
;
Ma, William Cheng-Yu
;
Kuo, Po-Yi
;
Wang, Kuan-Ti
In this paper, silicon-oxide-nitride-oxide-semiconductor (SONOS) devices with embedded silicon nanocrystals (Si-NCs) in silicon nitride using in situ method with multilevel and 2-b/cell operation have been successfully demonstrated. The proposed in situ Si-NC deposition method exhibits the advantages of low cost, simplicity, and compatibility with modern IC processes. SONOS memories with embedded Si-NCs exhibit a significantly improved performance with a large memory window (> 5.5 V), low operating voltage (P/E voltage: V(g) = 6 V, V(d) = 7 V and V(g) = -7 V, V(d) = 10 V, respectively), greater tolerable gate and drain disturbance (V(t) shift < 0.2 V), negligible second-bit effect, high P/E speed (after programming time = 10 mu s with a 2-V shift of V(t) under V(g) = V(d) = 6 V operation), good retention time (> 10(8) s for 13% charge loss), and excellent endurance performance (after 10(4) P/E cycles with a memory window of 3 V).
High-performance poly-Si TFT with ultra-thin channel film and gate oxide for low-power application
(2015-10-01)
Chen, Yi-Hsuan
;
Ma, William Cheng-Yu
;
Chao, Tien-Sheng
;
電子物理學系
;
Department of Electrophysics
In this paper, an ultra-thin-body thin-film transistor (UTB-TFT) with a raised source/drain structure is demonstrated and compared with a conventional thin-film transistor. A significant suppression of leakage current and an improvement in subthreshold swing (SS) resulting from the reduced body thickness is observed. The minimum current can be decreased from 245 pA to 42 pA as the channel film thickness is scaled down from 60 nm to 10 nm. However, an ultra-thin-channel film constrains the average grain size and severely impacts the saturation current. Fortunately, by decreasing the gate oxide thickness from 20 nm to 10 nm, the saturation current of a UTB-TFT can be significantly increased from 13 mu A to 25 mu A. Experimental results suggest that UTB-TFTs with a sub-10 nm gate oxide display great promise for future low-power, high-performance three-dimensional integrated circuits.
Impact of Crystallization Method on Poly-Si Tunnel FETs
(2015-10-01)
Chen, Yi-Hsuan
;
Ma, William Cheng-Yu
;
Lin, Jer-Yi
;
Lin, Chun-Yen
;
Hsu, Po-Yang
In this letter, the impact of crystallization method on the electrical characteristics of polycrystalline silicon (poly-Si) tunnel field-effect transistors (TFETs) is investigated. Different crystallization methods may result in different amounts of interface traps (N-it) and bulk traps (N-GB). TFETs crystallized with solid-phase crystallization (SPC) and metal-induced lateral crystallization (MILC) were fabricated and compared. In comparison with the SPC TFETs, the MILC TFETs exhibit similar to 4.5x higher ON-state current I-ON, subthreshold swing reduction Delta S.S. similar to 202 mV/decade, and larger similar to 7.2x ON/OFF current ratio. According to the measurement of a monitor poly-Si thin-film transistor, replacing SPC with MILC results in a reduced N-it similar to 0.60x and a reduced N-GB similar to 0.36x, respectively. It can enhance the gate-to-tunnel junction controllability. Consequently, lowering trap density favors reducing power consumption of TFETs and provides a promising solution for future low-power driving circuits in portable electronics.
Low temperature Ni-nanocrystals-assisted hybrid polycrystalline silicon thin film transistor for non-volatile memory applications
(2010-10-01)
Wang, Terry Tai-Jui
;
Ma, William Cheng-Yu
;
Hung, Shih-Wei
;
Kuo, Cheng-Tzu
;
材料科學與工程學系
The nickel-nanocrystals (Ni-NCs)-embedded silicon nitride acting as a trapping layer has been successfully demonstrated to manipulate the charging and discharging of electrons in a thin film transistor (TFT) for nonvolatile memory (NVM) applications. Regarding device performance, with and without Ni-NCs in the stack and under a programming/erasing condition of +/-18 V for 1 s, a better threshold voltage shift of 3.2 V can be reached compared to a shift of 2.0 V for a stack without Ni-NCs. The shift is an index representing the value required to differentiate "0" or "1" states during operation. In this case, the diameter range and number density of Ni-NCs are 5-13 nm and 5.3 x 10(11) cm(-2), respectively. (C) 2010 Elsevier B.V. All rights reserved.
Low temperature Ni-nanocrystals-assisted hybrid polycrystalline silicon thin film transistor for non-volatile memory applications
(2010-10-01)
Wang, Terry Tai-Jui
;
Ma, William Cheng-Yu
;
Hung, Shih-Wei
;
Kuo, Cheng-Tzu
;
材料科學與工程學系
The nickel-nanocrystals (Ni-NCs)-embedded silicon nitride acting as a trapping layer has been successfully demonstrated to manipulate the charging and discharging of electrons in a thin film transistor (TFT) for nonvolatile memory (NVM) applications. Regarding device performance, with and without Ni-NCs in the stack and under a programming/erasing condition of +/-18 V for 1 s, a better threshold voltage shift of 3.2 V can be reached compared to a shift of 2.0 V for a stack without Ni-NCs. The shift is an index representing the value required to differentiate "0" or "1" states during operation. In this case, the diameter range and number density of Ni-NCs are 5-13 nm and 5.3 x 10(11) cm(-2), respectively. (C) 2010 Elsevier B.V. All rights reserved.
Low-Temperature Polycrystalline Silicon Thin Film Transistor Nonvolatile Memory Using Ni Nanocrystals as Charge-Trapping Centers Fabricated by Hydrogen Plasma Process
(2010)
Wang, Terry Tai-Jui
;
Gao, Pei-Ling
;
Ma, William Cheng-Yu
;
Kuo, Cheng-Tzu
;
材料科學與工程學系
Processes for fabricating a Ni nanocrystal (NC)-assisted low-temperature polycrystalline silicon thin film transistor (LTPS-TFT) nonvolatile memory device of noble stack below 600 degrees C were successfully developed. The NCs were fabricated in H-plasma atmosphere by heating a nanosized Ni film to realize an appropriate nanoparticle distribution. Results show that NCs with a number density of similar to 5 x 10(11) cm(-2) and a particle diameter of 4 to 12 nm can successfully be fabricated as charge-trapping centers for enhancing the device performance. The results also indicate that the data retentions at the initial time and after 10(4) s for a SiO(2)/Ni-NCs/Si(3)N(4)/SiO(2) gate under the present stack of devices are about 2.2 and similar to 1.1 V, respectively. (C) 2010 The Japan Society of Applied Physics
Oxide Thinning and Structure Scaling Down Effect of Low-Temperature Poly-Si Thin-Film Transistors
(2012-01-01)
Ma, William Cheng-Yu
;
Chiang, Tsung-Yu
;
Lin, Je-Wei
;
Chao, Tien-Sheng
;
電子物理學系
In this paper, the gate oxide thickness, and the channel length and width of low-temperature poly-Si thin-film transistors (LTPS-TFTs) have been comprehensively studied. The scaling down of gate oxide thickness from 50 to 20 nm significantly improves the subthreshold swing (S. S.) of LTPS-TFTs from 1.797 V/decade to 0.780 V/ decade and the threshold voltage V(TH) from 10.87 V to 5.00 V. Moreover, the threshold voltage V(TH) roll-off is also improved with the scaling down of gate oxide thickness due to gate capacitance density enhancement. The channel length scaling down also shows significant subthreshold swing S. S. improvement due to a decreasing of the channel grain boundary trap density. However, the scaling down of channel length also increases the series resistance effect, resulting in the degradation of the field-effect mobility mu(FE). Therefore, the channel length dependence of field-effect mobility mu(FE) is slightly different with different channel width due to the competition of channel grain boundary trap density effect and series resistance effect.
Performance improvement of poly-Si tunnel thin-film transistor by NH3 plasma treatment
(2016-11-01)
Ma, William Cheng-Yu
;
Chen, Yi-Hsuan
;
Lin, Zheng-Yi
;
Huang, Yao-Sheng
;
Huang, Bo-Siang
In this paper, low-temperature polycrystalline silicon (poly-Si) tunnel thin-film transistors (tunnel-TFTs) are demonstrated to show excellent short-channel effects immunity due to their special current transport mechanism: inter-band tunneling. The ammonia (NH3) plasma surface treatment before the deposition of gate dielectric can significantly reduce the grain boundary trap state densities (N-GB) of poly-Si channel film and the interface trap state densities (N-it) at the gate-oxide/poly-Si interface. About 27% reduction of N-GB by NH3 plasma surface treatment can reduce the minimum drain current similar to 0.51x and improve the subthreshold slope due to the suppression of trap-assisted tunneling, which dominates the current transport in the subthreshold operation region. In addition, about 37% reduction of N-it by NH3 plasma surface treatment can significantly enhance the on-state current similar to 2.86x due to the increase of band bending of poly-Si channel potential, which can decrease the tunneling distance to increase the electron tunneling probability. Consequently, the performance improvement of poly Si tunnel-TFTs by the NH3 plasma surface treatment would be helpful for the development of system-on-panel and three-dimension integrated circuits. (C) 2016 Elsevier B.V. All rights reserved.
Performance improvement of poly-Si tunnel thin-film transistor by NH3 plasma treatment
(2016-11-01)
Ma, William Cheng-Yu
;
Chen, Yi-Hsuan
;
Lin, Zheng-Yi
;
Huang, Yao-Sheng
;
Huang, Bo-Siang
In this paper, low-temperature polycrystalline silicon (poly-Si) tunnel thin-film transistors (tunnel-TFTs) are demonstrated to show excellent short-channel effects immunity due to their special current transport mechanism: inter-band tunneling. The ammonia (NH3) plasma surface treatment before the deposition of gate dielectric can significantly reduce the grain boundary trap state densities (N-GB) of poly-Si channel film and the interface trap state densities (N-it) at the gate-oxide/poly-Si interface. About 27% reduction of N-GB by NH3 plasma surface treatment can reduce the minimum drain current similar to 0.51x and improve the subthreshold slope due to the suppression of trap-assisted tunneling, which dominates the current transport in the subthreshold operation region. In addition, about 37% reduction of N-it by NH3 plasma surface treatment can significantly enhance the on-state current similar to 2.86x due to the increase of band bending of poly-Si channel potential, which can decrease the tunneling distance to increase the electron tunneling probability. Consequently, the performance improvement of poly Si tunnel-TFTs by the NH3 plasma surface treatment would be helpful for the development of system-on-panel and three-dimension integrated circuits. (C) 2016 Elsevier B.V. All rights reserved.