Impact of Crystallization Method on Poly-Si Tunnel FETs

Abstract

In this letter, the impact of crystallization method on the electrical characteristics of polycrystalline silicon (poly-Si) tunnel field-effect transistors (TFETs) is investigated. Different crystallization methods may result in different amounts of interface traps (N-it) and bulk traps (N-GB). TFETs crystallized with solid-phase crystallization (SPC) and metal-induced lateral crystallization (MILC) were fabricated and compared. In comparison with the SPC TFETs, the MILC TFETs exhibit similar to 4.5x higher ON-state current I-ON, subthreshold swing reduction Delta S.S. similar to 202 mV/decade, and larger similar to 7.2x ON/OFF current ratio. According to the measurement of a monitor poly-Si thin-film transistor, replacing SPC with MILC results in a reduced N-it similar to 0.60x and a reduced N-GB similar to 0.36x, respectively. It can enhance the gate-to-tunnel junction controllability. Consequently, lowering trap density favors reducing power consumption of TFETs and provides a promising solution for future low-power driving circuits in portable electronics.