Browsing by Author "Nieh, YC"

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A hardware-efficient architecture for 3-D graphics processor
(1995)
Liang, BS
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Nieh, YC
;
Niou, YP
;
Jen, CW
;
Chuang, G
In 3-D graphics processor, large associated information per pixel cause storage and bus transfer problems in pixel operations. In this paper, we explore the parallelisms in pixel information to design a hardware-efficient architecture, hence the hardware cost of redundant registers in pipeline stages and unnecessary bus transfer can be saved.
An area and time efficient adder for multiple additions with different word-length
(1997)
Liang, BS
;
Nieh, YC
;
Jen, CW
;
交大名義發表
;
電子工程學系及電子研究所
To calculate multiple independent additions with different word-length by hardware sharing, we propose a new adder architecture in this paper, named self carry routing adder (SCRA). Multiple additions for data with different precision are usually occurring in some applications, like DDA operation in 3-D graphics rendering. By segmentation, rearrangement and dynamic carry routing, SCRA design can effectively decrease the delay time, reduce hardware area, and achieve high hardware utilization.