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Browsing by Author "Niou, YP"

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    A hardware-efficient architecture for 3-D graphics processor
    (1995)
    Liang, BS
    ;
    Nieh, YC
    ;
    Niou, YP
    ;
    Jen, CW
    ;
    Chuang, G
    In 3-D graphics processor, large associated information per pixel cause storage and bus transfer problems in pixel operations. In this paper, we explore the parallelisms in pixel information to design a hardware-efficient architecture, hence the hardware cost of redundant registers in pipeline stages and unnecessary bus transfer can be saved.