Browsing by Author "Shao, Chi-Shen"

Now showing 1 - 6 of 6

Back-gate bias effect on nanosheet hybrid P/N channel of junctionless thin-film transistor with increased I-on versus decreased I-off
(2015-11-02)
Cheng, Ya-Chi
;
Chen, Hung-Bin
;
Chang, Chun-Yen
;
Wu, Yi-Kang
;
Shih, Yi-Jia
A hybrid P/N channel junctionless (JL) thin-film transistor (TFT) with back-gate bias (V-bg) has been demonstrated. By applying negative bias of V-bg = -8V in gate length of 50 nm shows excellent SS (<90 mV/dec), a negligible drain induced barrier lowering (DIBL), increased I-on versus decreased I-off (ratio > 10(8)), and high V-th modulation. The increased I-on simultaneously decreased I-off via negative V-bg is attributed to smaller surface E-field at ON-state, significantly reducing the impact on interface traps and thinner effective channel thickness at OFF-state, improving gate controllability. Hence, hybrid P/N JL-TFT with V-bg is a promising for low power circuit, power management, and System-on-Chip applications. (C) 2015 AIP Publishing LLC.
Characteristics of a Novel Poly-Si P-Channel Junctionless Thin-Film Transistor With Hybrid P/N-Substrate
(2015-02-01)
Cheng, Ya-Chi
;
Chen, Hung-Bin
;
Su, Jun-Ji
;
Shao, Chi-Shen
;
Thirunavukkarasu, Vasanthan
This letter for the first time proposes a hybrid P/N substrate as a poly-Si p-channel for junctionless thin-film transistor (JL-TFT) with nanowires and omega-gate structures. The hybrid P/N JL-TFT exhibits a high I-ON/I-OFF current ratio (>10(7)), a steep subthreshold swing of 64 mV/dec, and a low drain-induced barrier lowering value of 3 mV/V by reducing the effective channel thickness that is caused by the channel/substrate junction. In addition, the series resistance for novel P/N JL-TFT with channel thickness (T-ch) of 24 nm is 50 times smaller than conventional JL-TFT with T-ch = 12 nm. This hybrid P/N structure can break through the strict limitation of JL-TFT channel thickness.
Characterizing the electrical properties of raised S/D junctionless thin-film transistors with a dual-gate structure
(2014-12-11)
Cheng, Ya-Chi
;
Chen, Hung-Bin
;
Su, Jun-Ji
;
Shao, Chi-Shen
;
Wang, Cheng-Ping
This letter demonstrates a p-type raised source-and-drain (raised S/D) junctionless thin-film transistors (JL-TFTs) with a dual-gate structure. The raised S/D structure provides a high saturation current (> 1 mu A/mu m). The subthreshold swing (SS) is 100 mV/decade and the drain-induced barrier lowering (DIBL) is 0.8 mV/V, and the I-on/I-off current ratio is over 10(8) A/A for L-g = 1 mu m. Using a thin channel structure obtains excellent performance in the raised S/D structure. Besides the basic electrical characteristics, the dual-gate structure can also be used to adjust V-th in multi-V-th circuit designs. This study examines the feasibility of using JL-TFTs in future three-dimensional (3D) layer-to-layer stacked high-density device applications.
Performance Enhancement of a Novel P-type Junctionless Transistor Using a Hybrid Poly-Si Fin Channel
(2014)
Cheng, Ya-Chi
;
Chen, Hung-Bin
;
Shao, Chi-Shen
;
Su, Jun-Ji
;
Wu, Yung-Chun
The hybrid poly-Si fin channel junctionless (JL) field-effect transistors (FET) are fabricated first. This novel devices show stable temperature/reliability characteristics, and excellent electrical performances in terms of a steep SS (64mV/dec), a high I-on/I-off current ratio (>10(7)) and a small DIBL (3mV/V) by reducing the effective channel thickness that is caused by the hybrid P+ channel and n-type substrate (hybrid P/N) junction. In addition, the novel P/N JL-TFT shows smaller series resistance and less current crowding than convectional JL-TFT with ultra-thin channel. Furthermore, our device can be supported by simulated results using technology computer-aided design (TCAD) simulation. Hence, the proposed hybrid P/N JL-TFTs are highly promising for future further scaling.
Temperature dependence of electronic behaviors in quantum dimension junctionless thin-film transistor
(2014-08-13)
Cheng, Ya-Chi
;
Chen, Hung-Bin
;
Han, Ming-Hung
;
Lu, Nan-Heng
;
Su, Jun-Ji
The high temperature dependence of junctionless (JL) gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with 2-nm-thick nanosheet channel is compared with that of JL planar TFTs. The variation of SS with temperature for JL GAA TFTs is close to the theoretical value (0.2 mV/dec/K), owing to the oxidation process to form a 2-nm-thick channel. The bandgap of 1.35 eV in JL GAA TFTs by fitting experimental data exhibits the quantum confinement effect, indicating greater suppression of I-off than that in JL planar TFTs. The measured partial derivative V-th/partial derivative T of -1.34 mV/degrees C in JL GAA nanosheet TFTs has smaller temperature dependence than that of -5.01 mV/degrees C in JL planar TFTs.
Temperature-dependent characteristics of junctionless bulk transistor
(2013-09-23)
Han, Ming-Hung
;
Chen, Hung-Bin
;
Yen, Shiang-Shiou
;
Shao, Chi-Shen
;
Chang, Chun-Yen
The temperature-dependent performance, including drain current (I-d) and gate capacitance (C-gg) of multi-gate junctionless (JL) bulk transistor for temperature (T) ranging from 150 K to 500 K, was investigated using 3D thermodynamic quantum-corrected device simulation. The combination effect of impurity scattering and phonon scattering is observed owing to the different temperature-dependent of mobility at low and high temperature. Since the C-gg of the JL device consists of a series combination of oxide capacitance (C-ox) and semiconductor channel capacitance (C-S) due to bulk conduction of the current, the C-gg at on-state (V-g = 1 V) shows much sensitive to the temperature than a conventional inversion-mode transistor. (C) 2013 AIP Publishing LLC.