Browsing by Author "Sheu, JT"

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A new fabrication technique for silicon nanowires
(2004-06-01)
Sheu, JT
;
Kuo, JM
;
You, KS
;
Chen, CC
;
Chang, KM
A new method is proposed for fabricating silicon nanowires (SiNWs) on silicon substrates instead of on SOI wafers, providing a cheaper process; it also enables their electrical properties to be measured easily. Using scanning probe lithography, mask patterns for SiNWs were defined on a (110)-oriented bare silicon wafer. Subsequently silicon nitride spacers were produced and utilized to protect SiNWs during a dry-oxidation process, which was applied to isolate the SiNWs from the substrate. The field induced oxide mask patterns generated with a scanning probe microscope were around 50-60 mn in width, and SiNWs with 34 nm in width and 160 nm in height resulted after wet potassium hydroxide (KOH) orientation-dependent etching at 40degrees for 400 s. SiNWs with line width around 34 mn on the bare silicon wafer were achieved with the scanning probe lithography process and conventional IC processing. (C) 2004 Elsevier B.V. All rights reserved.
An alternative process for silicon nanowire fabrication with SPL and wet etching system
(2004)
Chang, KM
;
You, KS
;
Lin, JH
;
Sheu, JT
;
電子工程學系及電子研究所
Silicon nanowire fabrication of nanoscale dimensions on a single-crystal silicon surface by scanning probe lithography (SPL) and potassium hydroxide (KOH) aqueous wet etching system has proven to be adequate technological processes. Using SPL directly to define patterns on a single-crystal silicon surface showed that the linewidth of similar to50 nm can be further shrunk to similar to20 nm with KOH wet etching and orientation-dependent etching (ODE) processes on (110)-oriented silicon samples. In addition, this lithography technique also showed a great ability to define patterns on fluorocarbon mask layers. This method performed the fine linewidth of silicon nanowires around 20 nm by operating with lower applied voltages and higher scanning speeds (shorter exposure time) with SPL and ODE techniques and KOH wet etching on (100)-oriented silicon samples. These alternative processes provide the capability to fabricate nanoscale structures with high reliability and repeatablility for applications in the nanofields. (C) 2004 The Electrochemical Society.
Characterization and lithographic parameters extraction for the modified resists
(1999)
Ko, FH
;
Lu, JK
;
Chu, TC
;
Huang, TY
;
Yang, CC
The modification of the i-line resist structure after spiking with various amount of poly(4-vinylphenol) polymer is characterized by the spectra of ultraviolet visible (UV-VIS) and gel permeation chromatography (GPC). The chemical structure of photoactive compound is found to be unchanged after modification, while slight change in the polymer chain is observed. The resist layer coated onto the wafer is characterized by various methods including n&k analyzer, Nanospec, Fourier transform infrared red (FTIR), thermogravimetric analysis (TGA), and differential scanning calorimetry (DSC) to fully evaluate the film properties in terms of porosity, thickness, vibrational spectrum, and thermal stability. Our thermal analysis results show that the resists are mainly decomposed in three stages. The photoactive compound (PAC) is found to decompose during the first stage, while the polymer decomposes during the latter stages. The resist exposure parameters, namely, A, B and C at 365 mn are determined by the absorbance measurement. The extracted parameters are further used in the resist profile simulation by PROLITH/2. It is shown that the spiking of poly(4-vinylphenol) polymer into the resist can improve the resolution and linearity for dense lines. In addition, the swing effects can be reduced by up to 35 and 31 % for dense and isolated lines after resist modification, respectively.
Direct Patterning of low-k hydrogen silsesquioxane using X-ray exposure technology
(2003-05-01)
Chang, TC
;
Tsai, TM
;
Liu, PT
;
Mor, YS
;
Chen, CW
An inorganic low-k material, hydrogen silsesquioxane (HSQ), patterned directly using X-ray exposure technology was investigated. In conventional integrated circuit integration processes, photoresist (PR) stripping with O-2 plasma and wet chemical stripper are inevitable steps. However, dielectric degradation often occurs when low-k dielectrics undergo PR stripping processes. To overcome the integration issue X-ray direct patterning is proposed. In this technology, the dielectric regions illuminated by X-ray are cross-linked and form desired patterns, while the regions without X-ray illumination are dissolvable in the solvent of HSQ solution. An optical microscope image of an HSQ linear pattern was demonstrated for the first time to verify process feasibility. (C) 2003 The Electrochemical Society.
Direct Patterning of low-k hydrogen silsesquioxane using X-ray exposure technology (vol 6, pg G69, 2003)
(2003-07-01)
Chang, TC
;
Tsai, TM
;
Liu, PT
;
Mor, YS
;
Chen, CW
Fabrication and electrical characterization of nanoscaled-Schottky diodes based on metal silicide/silicon nanowires with scanning probe lithography and wet etching
(2006-04-01)
Sheu, JT
;
Yeh, SP
;
Lien, CH
;
Tsai, ST
;
材料科學與工程學系奈米科技碩博班
Nanometer-sized Schottky diodes based on nickel monosilicide (NiSi)/silicon nanowire (SiNW) heterojunction have been fabricated and studied for their electrical transport characteristics. The SiNW was fabricated by scanning probe lithography (SPL) and tetramethylammonium (TMAH) wet etching. The diameter and height of the SiNWs were 60 and 25 nm, respectively. A Schottky barrier diode was obtained by patterning nickel film onto half of the SiNW by conventional lithography, and then forming nickel monosilicide by the solid state reaction between nickel and silicon under rapid thermal annealing (RTA) in N-2 ambient for 1 min. The current-voltage characteristics measured exhibited clear rectifying behavior consistent with a 0.22 eV schottky barrier height, and no reverse bias breakdown was observed up to a voltage of -5 V.
Fabrication of intermediate mask for deep x-ray lithography
(1998-02-01)
Sheu, JT
;
Chiang, MH
;
Su, S
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents the fabrication of intermediate x-ray mask for deep x-ray lithography. In order to have working mask with absorbers thickness larger than 10 mu m, the intermediate mask should have absorbers of 0.7 mu m in thickness. To demonstrate intermediate mask fabrication, x-ray zone plates are fabricated on the 1.2 mu m low-stress silicon-rich silicon nitride (SiNx) membrane with the tri-layer Chromium-Tungsten-Chromium (Cr-W-Cr) as the x-ray absorbers. The chromium layers both 200 angstroms are used as adhesion and for stress relief. The SiNx film is deposited with low pressure chemical vapor deposition (LPCVD) and the free standing membrane are formed by KOH silicon backside etching. With the e-beam Lithography and reactive ion etching, width of 0.8 mu m of outmost zone of the x-ray zone plates has been achieved on the membrane, The scanning electron microscopy (SEM) images of the x-ray zone plates and pictures of intermediate masks are demonstrated.
Nanoflash device with self-aligned double floating gates using scanning probe lithography and tetramethylammonium hydroxide wet etching
(2004-11-01)
Sheu, JT
;
Chen, CC
;
You, KS
;
Tsai, ST
;
材料科學與工程學系奈米科技碩博班
We report a self-aligned technology for nanoflash devices with double floating gates using scanning probe lithography (SPL) technology and anisotropic wet etching. On a (110) SOI silicon wafer, along [001] and [111] directions, a silicon nanowire was generated through local oxidation with SPL followed by wet etching with tetramethylammonium hydroxide solution. Silicon nanowires (SiNW) with profiles of sidewall either sloped or vertical were formed after anisotropic etching in the [001] or [111] direction respectively. After deposition of a polysilicon film on the SiNW with low pressure chemical vapor deposition, nanostructures of a nanoflash device with polysilicon double-floating side gates were obtained along the [111] part of SiNW after reactive ion etching spacer etching. The silicon nanowire channel has a width of 20 nm and a height of 200 rim; the width of the self-aligned floating gate is approximately 40 rim. Silicon nitride was deposited to serve as gate dielectric. The top gate and source-drain aluminum pads were defined by photo litholgraphy. Electrical properties of such a nanoflash device with double-floating side gates are discussed. (C) 2004 American Vacuum Society.
Selective deposition of gold nanoparticles on SiO(2)/Si nanowires for molecule detection
(2005-04-01)
Sheu, JT
;
Chen, CC
;
Huang, PC
;
Lee, YK
;
Hsu, ML
The selective deposition of gold nanoparticles on the surface of N-(2-Aminoethyl)-3-aminopropyl-trimethoxysilane (AEAPTMS)-pretreated silicon nanowire (SiNW)s for molecule detection was demonstrated. The SiNWs were fabricated by scanning probe lithography (SPL) and tetramethyl ammonium hydroxide (TMAH) wet etching. The width and height of the SiNWs were 60 nm and 10 nm, respectively. The gold nanoparticles were synthesized by the chemical reduction method. The electronic properties of the SiNWs in response to the binding of different molecules on the surface of the SiNWs subsequently were discussed. A dynamic observation of the change in conductance was conducted to monitor the reaction between gold nanoparticles and the AEAPTMS-pretreated surface of the SiNWs. The reaction of gold nanoparticles on the surface of the SiNWs took about 750 s before conductance saturation. Finally, an engineered enzyme, KSI-126C, with a thiol terminal was designed to bind with the gold nanoparticles on the surface of the SiNWs. Shifts in turn-on voltage in I-V(ds) characteristics have clearly been observed after the binding of molecules and gold nanoparticles.
Selective deposition of gold nanoparticles on SiO2/Si nanowire
(2005-03-01)
Sheu, JT
;
Chen, CC
;
Huang, PC
;
Hsu, ML
;
材料科學與工程學系奈米科技碩博班
We demonstrate selective deposition of citrate-passivated gold nanoparticles onto silicon dioxide patterns. Further, selective deposition of gold nanoparticles on the oxides, generated by scanning probe lithography (SPL). surface of silicon nanowire is achieved. Main methodology is to form H-terminated silicon surface and hydroxyl group on SiO2 sample surface, then link amino function group only on SiO2 surface by self-assembly mechanism. N-(2-Aminoethyl)-3-aminopropyl-trimethoxysilane (AEAPTMS) pretreated sample was immersed in the gold colloidal solution such that the NH2 group become protonated forming NH3+. The NH3+ groups provide a negative charge bindable environment for citrate-passivated gold nanoparticles. Impact on different AEAPTMS dilute solvents is also investigated for the performance of selective deposition of gold nanoparticles. It is found that H-terminated sample surface effectively eliminated nonspecific reaction during silanization such that microscale or nanoscale selective deposition of gold nanoparticles is obtainable. The proposed method can be applied in both nanoelectronics and nanobiosensors. (c) 2005 Elsevier B.V. All rights reserved.
Selective deposition of gold particles on dip-pen nanolithography patterns on silicon dioxide surfaces
(2006-04-01)
Sheu, JT
;
Wu, CH
;
Chao, TS
;
材料科學與工程學系奈米科技碩博班
;
電子物理學系
We report a novel platform to perform selective deposition of gold nanoparticles on dip-pen nanolithographic patterns on SiO2 surfaces. An "inked" atomic force microscope (AFM) tip was adopted to deposit 2.2mM organic N-(2-aminoethyl)-3aminopropyltriniethoxysilane (AEAPTMS) Molecules in nanopatterns through a water meniscus onto a SiO2, substrate under ambient conditions; the molecules act as linkers for the selective deposition of gold nanoparticles on the SiO2 surface. Conditions for dip-pen nanolithography of organic nanopatterns of AEAPTMS were investigated. In addition, gold nanoparticles with negatively-charged citrate Surfaces were deposited selectively on top of the organic patterns. X-ray photoelectron spectroscopy was then used to evaluate the presence of gold nanoparticles on the SiO2 surface. Lateral force microscopy was utilized to differentiate the surface between oxidized semiconductors and patterned areas with monolayer of AEAPTMS. Linewidths down to 60 nm have been successfully achieved by this method.
Selective growth of carbon nanotube on scanning probe tips by microwave plasma chemical vapor deposition
(2004-01-01)
Pan, FM
;
Liu, YB
;
Chang, Y
;
Chen, CY
;
Tsai, TG
We have selectively grown carbon nanotubes on the probe tip of an atomic force microscope by microwave plasma chemical vapor deposition. The catalyst domain was defined on the tip apex of an Si based scanning probe by local electric field induced oxidation of a TiN cap layer, under which the cobalt catalyst layer was predeposited on the probe surface. High resolution atomic force microscopy images of an SiO2 trench pattern are demonstrated using the carbon nanotube tip. The nanotube tip fabrication method is simple and compatible with existing thin film process technology. (C) 2004 American Vacuum Society.
Single-crystal silicon nanostructure fabrication by scanning probe lithography and anisotropic wet etching
(2001)
Chang, KM
;
You, KS
;
Wu, CH
;
Sheu, JT
;
電子工程學系及電子研究所
Silicon nanostructures have been demonstrated by electric-field-enhanced localized oxidation on single crystal silicon wafer using a scanning probe microscope (SPM). In this study, we have demonstrated the use of scanning probe lithography (SPL) and orientation-dependent etching (ODE) can easily obtain nano-wire and nano-gap down to 24nm and 60nm on (110)-oriented silicon substrate. The scanning probe lithography (SPL) provides high resolution, which can be adjusted by tip bias, tip set force, scanning speed, and ambient humidity of environment, without damage in the substrate. The etching process employed the orientation-dependent etching (ODE), because of the etching rate of the (Ill)-plane is slower than any other crystallographic planes such that anisotropic etching profile can be obtained. The experimental samples were hydrogen-passivated by dipping in 10% aqueous HF solution to remove sample native oxide on the surface before SPM localized oxidation process. The SiOx nano-patterns on (110)-oriented silicon substrate were generated by SPM localized oxidation. Then, the etching process employed the ODE with a 34 wt.% aqueous KOH solution. The nano-wire feature size is easily down to 24nm and aspect ratio larger than 4:1. The optimization fine/space nanostructure is about 20 nm/80 nm and the nano-gap is about 60nm. In this study, we also have demonstrated the influence of etching temperature on the feature size of nanostructures with same aspect ratio. At the same etching depth (100nm), the line-width decreases with increasing the etching temperature. The theoretic etching rate and experimental etching rate are proportional to temperature, the higher temperature the higher etching rate.
Single-electron transistor structures based on silicon-on-insulator silicon nanowire fabrication by scanning probe lithography and wet etching
(2002-11-01)
Sheu, JT
;
You, KS
;
Wu, CH
;
Chang, KM
;
電子工程學系及電子研究所
We propose a promising fabrication technology for single-electron transistors based on a silicon-on-insulator (SOI) nanowire fabricated by scanning probe lithography and KOH wet etching. The 10-nm-wide and 10-nm-high silicon nanowire is defined by scanning probe lithography and KOH wet etching process technology. Along the [100] direction on a (100) SOI silicon wafer, local oxidation was performed in ambient using highly doped Si cantilevers with a resistivity of 0.01-0.0025 Omega cm and a commercial atomic force microscope/scanning tunneling microscope instrument. Using the oxide pattern as a Si etching mask, the Si substrate was dipped in aqueous KOH solution, in which unoxidized regions are selectively etched by aqueous KOH orientation-dependent etching. The silicon nanowire was obtained by well-controlled overetching of 34 wt % at 40 degreesC for 50 s. The top gate, back gates and contact pads were defined by photolithography and dry etching. Statistics showing the reproducibility of this technique are also demonstrated. (C) 2002 American Vacuum Society.
The novel pattern method of low-k hybrid-organic-siloxane-polymer film using X-ray exposure
(2002-12-02)
Chang, TC
;
Tsai, TM
;
Liu, PT
;
Mor, YS
;
Chen, CW
An organic low dielectric constant (low-k) material, hybrid-organic-siloxane-polymer. (HOSP), is integrated into multilevel interconnection using X-ray exposure technology. In conventional IC integration processes, photoresist (PR) stripping with O-2 plasma and wet chemical stripper is an inevitable step. However, dielectric degradation often occurs when low-k dielectrics undergo the PR stripping process. This limits the application of incorporating low-k material into semiconductor fabrication. In order to overcome the integration issue, a novel pattern method, X-ray direct patterning is proposed. In this technology, the dielectric regions illuminated by X-ray will be cross-linked, forming the desired patterns. At the same time, the regions without X-ray illumination are dissolvable in a solvent of HOSP film. Direct-patterning processes have several advantages: (1) they do not need PR to define patterns; thereby the damage from PR stripping can be eliminated, (2) the complex etching on low-k dielectrics can be eliminated, (3) the process steps are simplified. In this work, we will investigate the dielectric properties of HOSP film with X-ray curing for the first time. Additionally, a scanning electron microscope image of circle pattern was made to verify the process practicability. (C) 2002 Elsevier Science B.V. All rights reserved.