Browsing by Author "Shieh, BJ"

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A generalized prediction method for modified memory-based high throughput VLC decoder design
(1999-06-01)
Lee, YS
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Shieh, BJ
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Lee, CY
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Variable-length code (VLC) is the most popular data-compression technique which has been used in many data-compression standards, such as JPEG, MPEG-2, and H.263, In this paper, we present a new memory-based tree-search algorithm and very large scale integration architecture for VLC decoders which can achieve very high decoding throughput performance. Different coding tables can be implemented by simply changing the contents of the memory without changing the system hardware, The coding table is mapped onto a memory whose space requirement has been minimized by using a new tree data structure and efficient memory-mapping strategy. In addition, we break the recursive dependency of iterative searching operations by predicting method. The proposed algorithm and architecture can predict the searching node and perform parallel operations. As a result, the decoding throughput rate can be enhanced to about three to eight times more than previously announced architecture. The proposed architecture mainly consists of memory modules and simple arithmetic unit. Based on 0.6-mu m single poly triple metal CMOS technology and MPEG-2 VLC table-15, the decoder system achieves average decoding throughput rate of 720 Mbits/s at 3 V and a 100-MHz clock rate.
A high throughput variable length decoder with modified memory based architecture
(1998)
Shieh, BJ
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Lee, YS
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Lee, CY
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Variable-Length Code (VLC) is the most popular data compression technique. Therefore, a high throughput Variable-Length Decoder (VLD) is required in many applications. In this paper, we propose 2 simple modified methods which can increase throughput of memory-based two-bit structure Variable-Length Decoder system [1]*. The additional hardware of modified architecture is some control unit and a little memory space. The overall system still consists of control unit, arithmetic unit and memory. Simulation results show that the decompression rate based on 0.6um CMOS process and MPEG2 coding table-15 can achieve 720M bits/s with 100MHz clock rate.
A high-throughput memory-based VLC decoder with codeword boundary prediction
(2000-12-01)
Shieh, BJ
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Lee, YS
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Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we present a high-throughput memory-based VLC decoder with codeword boundary prediction, The required information for prediction is added to the proposed branch models, Based on an efficient scheme, these branch models and the Huffman free structure are mapped onto memory modules, Taking the prediction information, the decompression scheme can determine the codeword length before the decoding procedure is completed. Therefore, a parallel-processor architecture can be applied to the VLC decoder to enhance the system performance. With a clock rate of 100 MHz, a dual-processor decoding process can achieve decompression rate up to 72.5 Msymbols/s on the average. Consequently, the proposed VLC decompression scheme meets the requirements of current and advanced multimedia applications.
A low-power group-based VLD design
(2004)
Liu, CH
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Shieh, BJ
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Lee, CY
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a low power variable length code decoder with group-based scheme [10] is proposed. It can save at most 70% power dissipation while maintaining the same throughput rate as the conventional one. This proposal mainly consists of look-up table (LUT) partitioning and group-based memory storing, where the former is used to reduce the power wasted on looking-up unnecessary code-words due to a large LUT, especially those code-words with low probability; the latter is used to reduce the storage space of VLC tables and maintain the flexibility of our hardware decoder.
A new approach of group-based VLC codec system with full table programmability
(2001-02-01)
Shieh, BJ
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Lee, YS
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Lee, CY
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, the algorithm and architecture of a variable-length-code (VLC) codec system using a new group-based approach and achieving full table programmability are presented. According to the proposed codeword grouping and symbol memory mapping, both group searching and encoding/decoding procedures are completed by applying numerical properties and arithmetic operations to codewords and symbol addresses, By a novel symbol conversion, the memory requirement of the encoding process is reduced and the programmability of codewords and symbols is achieved, For MPEG applications, a 0.6-mum CMOS design that performs concurrent VLC codec processes is shown. This VLSI implementation occupies an area of 5.0 x 4.5 mm(2) with 110 k transistors and satisfies a coding table up to 256-entry 12-bit symbols and 16-bit codewords, In addition, both encoding and decoding throughputs of this design achieve 100 Msymbols/s at a 100-MHz clock rate. Therefore, the proposed VLC codec system is suitable for applications which require high operation throughput, such as HDTV, and simultaneous compression and decompression, such as videoconferencing.
An all-digital phase-locked loop (ADPLL)-based clock recovery circuit
(1999-08-01)
Hsu, TY
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Shieh, BJ
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Lee, CY
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new algorithm for all-digital phase-locked loops (ADPLL) with fast acquisition and large pulling range is presented in this paper. Based on the proposed algorithm, portable cell-based implementations for clock recovery with functions of a frequency synthesizer and on-chip clock generator are completed by standard cell, These modules have been designed and verified on a 0.6-mu m CMOS process. Test results are summarized as follows: 1) the proposed ADPLL can satisfy full locked bandwidth and fast acquisition within one data transition; 2) the on-chip clack generator can generate any target clock rate f(clock); and 3) the function of nonreturn-to-zero clock recovery has a maximum f(clock)/4 recovering capability vith a locking range of (tau(input) + tau(input)/2), where tau(input) is the input period.
An efficient modeling codec architecture for binary shape coding
(2002)
Liu, TM
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Shieh, BJ
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Lee, CY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, the efficient modeling codec architecture for binary shape coding is presented. this novel design includes a memory unit that employs the Address Generation module and the Select & Barrel Shift module to speed up the process of border pixels generation. A simple architecture of the modified modeling unit, which uses a Column-scan map to reduce the number of mux and barrel shifter is proposed. Based on the proposed architecture, it deals with not only context computation of the intra mode but also it of the inter mode on the same hardware architecture. In addition, this design technique is suitable for the context-based arithmetic encode/decode in the whole MPEG4 codec system.