Browsing by Author "Shieh, Wuu-Trong"

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Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs
(2011-02-01)
Ker, Ming-Dou
;
Chen, Wen-Yi
;
Shieh, Wuu-Trong
;
Wei, I-Ju
;
電機學院
For integrated circuits (ICs) with voltage programming pin (V(PP) pin), a voltage higher than the normal power supply voltage of internal circuits is applied on the V(PP) pin to program the read-only memory (ROM). Because of the high programming voltage, the ESD diode placed from I/O pad to V(DD) cannot be applied to such V(PP) pin. In this work, a new ESD protection design is proposed to improve ESD robustness of V(PP) pin with the consideration of the mistriggering issue when V(PP) programming voltage has a fast rise time. In collaboration with the N-well ballast layout, the new proposed ESD protection design implemented in an IC product has been verified in a fully-silicided CMOS process to successfully achieve a high human-body-model ESD protection level of 5 kV.
ESD Protection Design for Touch Panel Control IC Against Latchup-Like Failure Induced by System-Level ESD Test
(2017-02)
Ker, Ming-Dou
;
Chiu, Po-Yen
;
Shieh, Wuu-Trong
;
Wang, Chun-Chi
;
電子工程學系及電子研究所
Due to the snapback holding voltage of high-voltage (HV) nMOS smaller than the maximum operating voltage, the traditional power-rail electrostatic discharge (ESD) clamp circuit implemented with such HV nMOS suffered latchup-like failure in a touch panel control IC after the system-level ESD test. A modified design on the power-rail ESD clamp circuit is proposed and verified in an HV CMOS process with 12 V double-diffused drain MOS device. With the holding voltage greater than the maximum operating voltage of 12 V, the touch panel equipped with the modified control IC can successfully pass the system-level ESD test of +/- 15 kV in the air-discharge test mode to meet the level 4 of IEC 61000-4-2 industry specification.
ESD-Induced Latchup-Like Failure in a Touch Panel Control IC
(2017-01-01)
Ker, Ming-Dou
;
Chiu, Po-Yen
;
Shieh, Wuu-Trong
;
Wang, Chun-Chi
;
電子工程學系及電子研究所
With on-chip ESD protection design, the I/O pins of a touch panel control IC can pass the chip-level ESD tests of HBM 4kV and MM 400V. However, such a touch panel control IC mounted onto a display panel suffered the latchup-like failure after the system-level ESD zapping in the air-discharge mode. Some high-voltage power pin began to generate a large leakage current after the system-level ESD test, which demonstrated a symptom of latchup failure. By failure analyses with TLP-measurement, EMMI, and SEM, the root cause has been found on the power-rail ESD clamp circuit of the high-voltage power pin. The holding voltage of the power-rail ESD clamp circuit in the high-voltage power pin, that was lower than its normal operating voltage, caused such a latchup-like failure. Some modified solutions to rescue this latchup-like failure in the touch panel control IC are presented.
New Ballasting Layout Schemes to Improve ESD Robustness of I/O Buffers in Fully Silicided CMOS Process
(2009-12-01)
Ker, Ming-Dou
;
Chen, Wen-Yi
;
Shieh, Wuu-Trong
;
Wei, I-Ju
;
電機學院
Silicidation has been reported to result in substantial negative impact on the electrostatic discharge (ESD) robustness of MOS field-effect transistors. Although silicide blocking (SB) is a useful method to alleviate ESD degradation from silicidation, it requires additional mask and process steps to somehow increase the fabrication cost. In this paper, two new ballasting layout schemes to effectively improve the ESD robustness of input/output (I/O) buffers with fully silicided NMOS and PMOS transistors have been proposed. Ballasting technique in layout is a cost-effective method to enhance the ESD robustness of fully silicided devices. Experimental results from real IC products have confirmed that the new ballasting layout schemes can successfully increase the HBM ESD robustness of fully silicided I/O buffers from the original 1.5 kV to over 6 kV without using the additional SB mask.