Browsing by Author "Su, ChauChin"

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A 1.5V 7.5uW Programmable Gain Amplifier for Multiple Biomedical Signal Acquisition
(2009)
Kao, Shuo-Ting
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Lu, Hungwen
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Su, ChauChin
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交大名義發表
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National Chiao Tung University
This paper presents a programmable analog front-end IC for multiple biomedical signal acquisition. By chopper-stabilized technique with an AC feedback circuit, the proposed circuit rejects differential electrode offset, common-mode disturbance and solves the problem of flicker noise. In TSMC 0.18 mu m CMOS process, the proposed circuit occupies an active area of 0.38mm(2). With digital controls, the voltage gain, low-pass and high-pass cutoff frequency could be adjusted in the range of 52db-88db, 0.5Hz-10Hz and 100Hz-400Hz, respectively. With a supply voltage of 1.5V, the proposed circuit achieves an input-referred noise of 90nV*Hz(boolean AND)-0.5, a noise-efficient factor of 6.1 while consuming a total current of 5 mu A.
A 5Gb/s Pulse Signaling Interface for Low Power On-Chip Data Communication
(2010)
Lin, Hung-Wen
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Ho, Ying-Chieh
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Fa, YingLin
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Su, ChauChin
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交大名義發表
This paper presents an on-chip pulse signaling scheme for low power on-chip interconnection. Both near-end and far-end employ equalization circuits to compensate the high frequency attenuation of long channel. The on-chip data bus is designed by co-planar micro-strip line in Metal 5 and Metal 6 and with a characteristic impedance of 75 ohm. The receiver uses self-biased inverters and transmission gates to design inductive-peaking and non-clock hysteresis amplifiers. In 0.13um CMOS process, the proposed I/O occupies a total area of 0.07mm(2). At a bit rate of 5Gbps, the accumulated peak-to-peak jitter of overall I/O system and a 5mm of channel length is 76ps. And it consumes 8mW of power under 1.2V supply voltage or with a power efficiency of 0.32pJ/bit/mm.
A Low-Power Analog-to-Digital Converter with Digitalized Amplifier for PAM Systems
(2014)
Ho, Yingchieh
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Kuo, Chou-Ming
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Su, ChauChin
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, we have proposed a 4-bit 5-GSample/s flash analog-to-digital converter (ADC) for pulse amplitude modulation (PAM) systems. In order to achieve low-power consumptions, digitalized cells for analogue amplifying are developed in the proposed ADC. Digitalized cells reduce power significantly due to using fewer devices as compared to pure analogue designs. A self-biasing circuit is used in the digitalized amplifier can enhance linear amplifying region. Besides, the digitalized amplifier can achieve high speed according to its bandwidth compensation technique. The test chip is implemented with 90nm CMOS Logic and Mixed-Mode 1P9M Low-K Process. The low-power digitalized ADC is operated under 5GSample/s. All the results of post-simulation are demonstrated in a 16-PAM system, and efficient number of bit is 3.9bit. Moreover, INL and DNL are less than 0.5LSB. The power consumption of the ADC is 33.7mW, and the FoM of energy per conversion step is only 0.45pJ. The overall chip area is 0.873mm(2).
A Scalable Digitalized Buffer for Gigabit I/O
(2008)
Lu, HungWen
;
Su, ChauChin
;
Liu, Chien-Nan
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交大名義發表
;
National Chiao Tung University
A serial I/O composed of inverters and transmission gates only is proposed to achieve high supply voltage scalability and low area overhead. The inverter with an inductive biasing circuit can extend bandwidth, and reduce the SSN simultaneously. With a TSMC 0.18 mu m CMOS process, the I/O occupies an area of 0.014mm(2) and operates from 4Gbps@1.9V to 1.5Gbps@1.1V.