Browsing by Author "Su, Chun-Jung"

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A junctionless SONOS nonvolatile memory device constructed with in situ-doped polycrystalline silicon nanowires
(2012-02-29)
Su, Chun-Jung
;
Su, Tuan-Kai
;
Tsai, Tzu-I
;
Lin, Horng-Chih
;
Huang, Tiao-Yuan
In this paper, a silicon-oxide-nitride-silicon nonvolatile memory constructed on an n(+)-poly-Si nanowire [NW] structure featuring a junctionless [JL] configuration is presented. The JL structure is fulfilled by employing only one in situ heavily phosphorous-doped poly-Si layer to simultaneously serve as source/drain regions and NW channels, thus greatly simplifying the manufacturing process and alleviating the requirement of precise control of the doping profile. Owing to the higher carrier concentration in the channel, the developed JL NW device exhibits significantly enhanced programming speed and larger memory window than its counterpart with conventional undoped-NW-channel. Moreover, it also displays acceptable erase and data retention properties. Hence, the desirable memory characteristics along with the much simplified fabrication process make the JL NW memory structure a promising candidate for future system-on-panel and three-dimensional ultrahigh density memory applications.
A novel multiple-gate polycrystalline silicon nanowire transistor featuring an inverse-T gate
(2008-07-01)
Lin, Horng-Chih
;
Hsu, Hsing-Hui
;
Su, Chun-Jung
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
A novel multiple-gate field-effect transistor with poly-Si nanowire (NW) channels is proposed and fabricated using a simple process flow. In the proposed structure, poly-Si NW channels are formed with sidewall spacer etching technique, and are surrounded by an inverse-T-gate and a top gate. When the two gates are connected together to drive the NW channels, dramatic performance enhancement as compared with the cases of single-gate operation is observed. Moreover, subthreshold swing as low as 103 mV/dec at Vd = 2 V is recorded. Function of using the top gate bias to modulate the threshold voltage of device operation driven by the inverse-T gate biases is also investigated in this letter.
A novel photoresist-based film-profile engineering scheme for fabricating double-gated, recess-channel IGZO thin-film transistors
(2020-04-01)
Huang, Yu-An
;
Peng, Kang-Pin
;
Meng, Yu-Chiao
;
Su, Chun-Jung
;
Li, Pei-Wen
We reported an experimental fabrication of double-gated (DG) thin-film transistor (TFT) with IGZO recess-channel using a designer photoresist-based thin-film profile engineering approach. In this approach, an organic shadow mask of photoresist (PR) was formed over a p(+)-Si wafer that was encapsulated by an oxide layer, The lithographically-patterned PR layer is an effective mask for shadowing reactive species during the subsequent deposition steps of IGZO and Aluminum, enabling the formation of IGZO recess-channel and discrete Al source/drain pads at room temperature. The top-gate or DG configurations with the Si substrate serving as the bottom-gate were investigated. The fabricated DG TFTs show significant; improvements in both I-ON and I-OFF as compared with single-gated TFTs. The proposed process scheme is readily applicable to the back-end-of-line of a chip. This work demonstrates the feasibility of IGZO recess-channel TFTs in various gated configurations, enabling a building block for emerging functional devices for More-than-Moore applications. (C) 2020 The Japan Society of Applied Physics
Characteristics of PBTI and hot carrier stress for LTPS-TFT with high-kappa gate dielectric
(2008-02-01)
Ma, Ming-Wen
;
Chen, Chih-Yang
;
Su, Chun-Jung
;
Wu, Woei-Cherng
;
Wu, Yi-Hong
In this letter, the characteristics of positive bias temperature instability (PBTI) and hot carrier stress (HCS) for the low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO2 gate dielectric are well investigated for the first time. Under room temperature stress condition, the PBTI shows a more serious degradation than does HCS, indicating that the gate bias stress would dominate the hot carrier degradation behavior for HfO2 LTPS-TFT. In addition, an abnormal behavior of the I-min degradation with different drain bias stress under high-temperature stress condition is also observed and identified in this letter. The degradation of device's performance under high-temperature stress condition can be attributed to the damages of both the HfO2 gate dielectric and the poly-Si grain boundaries.
Characterizations of polycrystalline silicon nanowire thin-film transistors enhanced by metal-induced lateral crystallization
(2012-11-01)
Su, Chun-Jung
;
Huang, Yu-Feng
;
Lin, Horng-Chih
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
In this paper, we present a comprehensive study on the effects of layout design and re-crystallization temperature on the material and electrical characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) with metal-induced lateral crystallized (MILC) nanowire (NW) channels. It is found that the off-state leakage current shows strong dependence on the arrangement of MILC seeding windows, while the number of smaller solid-phase-crystallized (SPC) grains in the channel is reduced by lowering the re-crystallization temperature, thus improving the on-state behavior. Moreover, owing to the spatial confinement for MILC fronts, small cross-section of the NW channel would result in little lateral crystallization, and thus retarding the enhancement in performance of MILC NW devices. (c) 2012 Elsevier Ltd. All rights reserved.
Effect of Ni residues on the performance and the uniformity of nickel-induced lateral crystallization polycrystalline silicon nanowire thin-film transistors
(2010-11-01)
Wang, Bau-Ming
;
Yang, Tzu-Ming
;
Wu, YewChung Sermon
;
Su, Chun-Jung
;
Lin, Horng-Chih
High performance nickel-induced lateral crystallization (NILC) polycrystalline silicon (poly-Si) nanowire (NW) thin-film transistors (TFTs) were fabricated. The phosphorous-doped amorphous silicon (alpha-Si)/chem-SiO(2) films were employed as Ni-gettering layers to investigate effect of Ni residues on the performance and the uniformity of NILC poly-Si NW TFTs. It was found that the performance and the uniformity of NW TFTs were greatly improved after Ni-gettering process. (C) 2010 Elsevier B.V. All rights reserved.
Effect of Ni residues on the performance and the uniformity of nickel-induced lateral crystallization polycrystalline silicon nanowire thin-film transistors
(2010-11-01)
Wang, Bau-Ming
;
Yang, Tzu-Ming
;
Wu, YewChung Sermon
;
Su, Chun-Jung
;
Lin, Horng-Chih
High performance nickel-induced lateral crystallization (NILC) polycrystalline silicon (poly-Si) nanowire (NW) thin-film transistors (TFTs) were fabricated. The phosphorous-doped amorphous silicon (alpha-Si)/chem-SiO(2) films were employed as Ni-gettering layers to investigate effect of Ni residues on the performance and the uniformity of NILC poly-Si NW TFTs. It was found that the performance and the uniformity of NW TFTs were greatly improved after Ni-gettering process. (C) 2010 Elsevier B.V. All rights reserved.
Effective N-methyl-2-pyrrolidone wet cleaning for fabricating high-performance monolayer MoS2 transistors
(2019-02-01)
Chen, Po-Chun
;
Lin, Chih-Pin
;
Hong, Chuan-Jie
;
Yang, Chih-Hao
;
Lin, Yun-Yan
Two-dimensional semiconductors, such as MoS2 are known to be highly susceptible to diverse molecular adsorbates on the surface during fabrication, which could adversely affect device performance. To ensure high device yield, uniformity and performance, the semiconductor industry has long employed wet chemical cleaning strategies to remove undesirable surface contaminations, adsorbates, and native oxides from the surface of Si wafers. A similarly effective surface cleaning technique for two-dimensional materials has not yet been fully developed. In this study, we propose a wet chemical cleaning strategy for MoS2 by using N-methyl-2-pyrrolidone. The cleaning process not only preserves the intrinsic properties of monolayer MoS2, but also significantly improves the performance of monolayer MoS2 field-effect-transistors. Superior device on current of 12 Am-1 for a channel length of 400 nm, contact resistance of 15 km, field-effect mobility of 15.5 cm(2)V(-1)s(-1), and the average on-off current ratio of 10(8) were successfully demonstrated
Effects of Annealing on Ferroelectric Hafnium-Zirconium-Oxide-Based Transistor Technology
(2019-03-01)
Chen, Yi-Hsuan
;
Su, Chun-Jung
;
Hu, Chenming
;
Wu, Tian-Li
;
國際半導體學院
In this letter, we investigate annealing effects in ferroelectric HfZrOx dielectric in metal-insulator-metal devices and metal-oxide-semiconductor capacitors by comparing two annealing methods: rapid thermal annealing (RTA) and microwave annealing (MWA). The tradeoff characteristics between the annealing conditions, polarization-electric field characteristics, gate leakage current, and interface state density (D-it) are discussed. We show that: 1) a positive correlation between the remanent polarization (Pr), the gate leakage current, and D-it as the annealing temperature (RTA) and the annealing power (MWA) increase and 2) the MWA is promising for ferroelectric transistors technology, since its low thermal budget can minimize D-it and avoid increase in the gate leakage current.
Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter
(2020-01-01)
Sung, Po-Jung
;
Su, Chun-Jung
;
Lo, Shih-Hsuan
;
Hsueh, Fu-Kuo
;
Lu, Darsen D.
In this study, ferroelectric FETs (FeFETs) and CMOS inverters are fabricated and analyzed, exhibiting 13% of 593 devices with sub-60 mV subthreshold swing (SS) at room temperature. Forming gas annealing (FGA) is found to not only enhance ferroelectricity but also significantly improve FeFET electrostatics. The experimental results indicate that FeFET with a narrow width shows weaker ferroelectric properties, and SS of sub-60 mV/dec with I-D change less than two orders of magnitude. However, FeFET with a broad channel width reveals stronger ferroelectric properties, and SS of sub-60 mV/dec is over 2 orders of magnitude of I-d. Finally, typical voltage transfer characteristics (VTCs) of a FeFET CMOS inverter with double sweeps at various V-D from 0.6 to 2 V are demonstrated. The results show that hysteresis in a FeFET CMOS inverter could have both clockwise (CW) and counter-clockwise (CCW) loops.
Fabrication and characterization of nanowire transistors with solid-phase crystallized poly-Si channels
(2006-10-01)
Lin, Horng-Chih
;
Lee, Ming-Hsien
;
Su, Chun-Jung
;
Shen, Shih-Wen
;
電子工程學系及電子研究所
The performance of thin-film transistors with a novel poly-Si nanowire channel prepared by solid-phase crystallization is investigated in this paper. As compared with conventional planar devices having self-aligned source/drain, the new devices show an improved ON-current per unit width and better control over the short channel effects. The major conduction mechanism of the OFF-state leakage is identified as the gate-induced drain leakage, and it is closely related to the source/drain implant condition and the unique device structure.
Fabrication and characterization of poly-Si nanowire devices with performance enhancement techniques
(2007)
Su, Chun-Jung
;
Lin, Homg-Chih
;
Tsai, Hsien-Hung
;
Huang, Tiao-Yuan
;
Ni, Wei-Xin
Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters
(2020-09-01)
Sung, Po-Jung
;
Chang, Shu-Wei
;
Kao, Kuo-Hsing
;
Wu, Chien-Ting
;
Su, Chun-Jung
In this study, conventional CMOS and complementary field-effect transistor (CFET) inverters based on a vertically stacked-nanosheet (NS) structure were fabricated. The NS below 8-nm channel layer thickness (T-Si) was obtained by dry etching and wet etching processes. The channel thickness is controlled by dry etching, and the channel width was shrunk down by wet etching. Compared to single nanowire field-effect transistors (NSFETs), stacked NSFETs exhibit higher ON-current performance. For the CMOS inverter, the voltage transfer characteristics (VTCs) could be matched much better by adjusting the channel widths and layers for N-channel MOSFET (NFET) and P-channel MOSFET (PFET), respectively. For the CFET inverter, layout areas could be reduced and requires less number of lithographic and ion implantation steps contrary to the CMOS inverter. However, we observe that the VTCs of the CFET inverters still show asymmetric behavior due to the difficulties of adjustment in NS layers and systematic behavior of threshold voltages for NFETs/PFETs. This work experimentally demonstrates the CMOS and CFET inverters on the vertically stacked NS structure, which is promising for system-on-panel (SoP) and 3-D-ICs applications.
Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels
(2011-04-01)
Su, Chun-Jung
;
Tsai, Tzu-I
;
Liou, Yu-Ling
;
Lin, Zer-Ming
;
Lin, Horng-Chih
In this letter, we have investigated experimentally, for the first time, the feasibility of gate-all-around polycrystalline silicon (poly-Si) nanowire transistors with junctionless (JL) configuration by utilizing only one heavily doped poly-Si layer to serve as source, channel, and drain regions. In situ doped poly-Si material features high and uniform-doping concentration, facilitating the fabrication process. The developed JL device exhibits desirable electrostatic performance in terms of higher ON/OFF current ratio and lower source/drain series resistance as compared with the inversion-mode counterpart. Such scheme appears of great potential for future system-on-panel and 3-D IC applications.
High-performance metal-induced laterally crystallized polycrystalline silicon p-channel thin-film transistor with TaN/HfO2 gate stack structure
(2008-06-01)
Ma, Ming-Wen
;
Chao, Tien-Sheng
;
Su, Chun-Jung
;
Wu, Woei-Cherng
;
Kao, Kuo-Hsing
In this letter, high-performance low-temperature poly-Si p-channel thin-film transistor with metal-induced lateral-crystallization (MILC) channel layer and TaN/HfO2 gate stack is demonstrated for the first time. The devices of low threshold voltage V-TH similar to 0.095 V, excellent subthreshold swing S.S. similar to 83 mV/dec., and high field-effect mobility mu(FE) similar to 240 cm(2)/V center dot s are achieved without any defect passivation methods. These significant improvements are due to the MILC channel film and the very high gate-capacitance density provided by HfO2 gate dielectric with the effective oxide thickness of 5.12 mn.
High-performance poly-Si nanowire NMOS transistors
(2007-03-01)
Lin, Horng-Chih
;
Su, Chun-Jung
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel field-effect transistor with Si nanowire (NW) channels is developed and characterized. To enhance the film crystallinity, metal-induced lateral crystallization (MILC) and/or rapid thermal annealing (RTA) techniques are adopted in the fabrication. In the implementation of MILC process, it is shown that the arrangement of seeding window plays an important role in affecting the resulting film structure. In this regard, asymmetric window arrangement, i.e., with the window locating on only one of the two channel sides is preferred. When MILC and RTA techniques are combined, it is found that single-crystal-like NWs are achieved, leading to significant performance improvement as compared with the control with channels made up of fine-grain structures by the conventional solid-phase, crystallized (SPC) approach. Field-effect mobility up to 550 cm(2)/V-s is recorded in this study.
Impact of the polarization on time-dependent dielectric breakdown in ferroelectric Hf0.5Zr0.5O2 on Ge substrates
(2020-04-01)
Yang, Ting-Hsin
;
Su, Chun-Jung
;
Wang, Yu-Shun
;
Kao, Kuo-Hsing
;
Lee, Yao-Jen
In this work, polarization-dependent time-dependent dielectric breakdown in ferroelectric HZO Ge MOSCAPs presented. First, ferroelectric HZO Ge MOSCAPs with and without in-situ NH3 plasma interfacial layer, treatment exhibit the two distinct remnant polarization (P-r), Secondly the device with a larger P-r shows a higher gate leakage current and smaller time-to-breakdown (t(BD)) compared to the device with a smaller P-r. Then, a physical model based on the high probability of the electron tunneling accelerating the formation of the percolation path is proposed. Finally, the device with large P-r shows a lower extrapolated operating voltage. However more than 1.5 V of the extracted operation voltage for 1% failure of 10 year lifetime in the device with large P-r still can be obtained. (C) 2020 The Japan Society of Applied Physics
Impacts of fluorine ion implantation with low-temperature solid-phase crystallized activation on high-kappa LTPS-TFT
(2008-02-01)
Ma, Ming-Wen
;
Chen, Chih-Yang
;
Su, Chun-Jung
;
Wu, Woei-Cherng
;
Wu, Yi-Hong
In this letter, fluorine ion implantation with low-temperature solid-phase crystallized activation scheme is used to obtain a high-performance HfO2 low-temperature poly-Si thin-film transistor (LTPS-TFT) for the first time. The secondary ion mass spectrometer (SIMS) analysis shows a different fluorine profile compared to that annealed at high temperature. About one order current reduction of I-min is achieved because 25% grain-boundary traps are passivated by fluorine implantation. In addition, the threshold voltage instability of hot carrier stress is also improved with the introduction of fluorine. The LTPS-TFT with HfO2 gate dielectric and fluorine preimplantation can simultaneously achieve low V-TH similar to 1.32 V, excellent subthreshold swing similar to 0.141 V/dec, and high I-ON/I-min current ratio 1.98 x 10(7).
Impacts of Multiple-Gated Configuration on the Characteristics of Poly-Si Nanowire SONOS Devices
(2011-03-01)
Hsu, Hsing-Hui
;
Lin, Horng-Chih
;
Luo, Cheng-Wei
;
Su, Chun-Jung
;
Huang, Tiao-Yuan
In this paper, we have proposed a simple and novel way to fabricate poly-Si nanowire (NW)-silicon-oxide-nitride-oxide-silicon (SONOS) devices with various gate configurations. Three types of devices having various gate configurations, such as side gated, O-shaped gated OG, and gate-all-around (GAA), were successfully fabricated and characterized. The experimental results show that, owing to the superior gate controllability over NW channels, much improved transfer characteristics are achieved with the GAA devices, as compared with the other types of devices. Moreover, GAA devices also exhibit the best memory characteristics among all splits, including the fastest programming/erasing efficiency, largestmemory window, and best endurance/retention characteristics, highlighting the potential of such scheme for future SONOS applications.
Impacts of nitric acid oxidation on low-temperature polycrystalline silicon TFTs with high-k gate dielectric
(2007)
Yang, Tsung-Yu
;
Ma, Ming-Wen
;
Kao, Kuo-Hsing
;
Su, Chun-Jung
;
Chao, Tien-Sheng
In this paper, low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFrs) with HfO2 gate dielectric and nitric acid oxidation pre-treatment is investigated. Significant improvement on on/off current ratio and field effect mobility is observed due to the nitric acid oxidation pre-treatment. An excellent on/off current ratio and subthreshold swing, as well as low threshold voltage and I-off can be achieved without any other hydrogen passivation treatments. These improved performances can be attributed to both the high gate capacitance density using high-k gate dielectric and the good interface quality by nitric acid oxidation of poly-silicon.