Browsing by Author "Su, Jen-Yi"

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0.13-mu M CMOS Q-BAND LEVELED-LO SUBHARMONIC MIXER WITH INJECTION-LOCKED FREQUENCY-DIVIDER QUADRATURE GENERATOR
(2009-11-01)
Su, Jen-Yi
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Meng, Chinchun
;
Wu, Po-Yi
;
Huang, Guo-Wei
;
電子工程學系及電子研究所
In this article, a 40-GHz subharmonic Gilbert down-conversion mixer with an accurate quadrature local oscillator (LO) input is demonstrated using a standard 0.13-mu m CMOS technology. The quadrature-output frequency divider is realized by injection-locked oscillators and is used at the LO port to replace conventional RC-CR polyphase filters at higher frequencies. Furthermore, the proper Marchand balun at all RF stage is suitable for the standard Si-based process to generate precisely balanced signals despite the substrate loss. The measured conversion gat In is 4 dB at 40 GHz. The IP(1dB) IIP(3) of - 7 dBm and 2 dBm, respectively, tire achieved. The measured 3-dB RF bandwidth is very broad and about 12-GHz bandwidth when the 10-MHz IF frequency is fixed. The die Size is about I mm X I mm. (C) 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2663-2665, 2009; Published online in Wiley InterScience (www.interscience.wiley.com), DOI 10.1002/mop.24714
16-GHz mHEMT Double-Quadrature Gilbert Down-Conversion Mixer With Polyphase Filters
(2013)
Hsiao, Yu-Chih
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Meng, Chinchun
;
Su, Jen-Yi
;
Yu, Sheng-Wen
;
Huang, Guo-Wei
A 16-GHz double-quadrature very low IF down conversion mixer with polyphase filters is demonstrated using 0.15-nm metamorphic high electron mobility transistor (mHEMT) technology. Due to the hgih cut-off frequency of mHEMT device, the image rejection Gilbert mixer works at 16 GHz. The polyphase filters are employed to generate differential quadrature signals and eliminate the image signal at RF/LO stages and IF stage, respectively, in the double quarture configuration. When RF and LO frequencies are designed around 16 GHz and an IF frequency is 32 MHz, The double-quadrature Gilbert down-converter has 32-dB image rejection ratio, 1.7-dB conversion gain, -5-dBm IP1dB, and 5-dBm IIP3. The die size is 3.0 mm x 3.2 mm.
16.4 GHz SiGe BiCMOS Sub-Harmonic Mixer With Reactive I/Q Generators in RF and LO Paths
(2009)
Tseng, Sheng-Che
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Syu, Jin-Siang
;
Su, Jen-Yi
;
Wei, Hung-Ju
;
Meng, Chinchun
This paper demonstrates a high-frequency 0.35-mu m SiGe BiCMOS sub-harmonic downconverter with reactive in-phase and quadrature-phase (I/Q) generators. Two reactive I/Q generators are integrated in our work to provide differential quadrature RI and LO signals. The I/Q sub-harmonic downconverter with single-ended LO, RI, and IF (IM) ports has a conversion gain of 1 dB, IP(1dB) of -10 dBm, IIP(3) of 0 dBm and IIP(2) of 21 dBm at 16.4 GHz. The magnitude and phase errors between the I and Q channels are 1.34% and 0.6 degrees, respectively. The dc power consumption of this I/Q mixer without output buffers is approximately 5 mW.
17-GHz pHEMT Gilbert Single-Quadrature Downconverter With Polyphase Filters for Image Rejection
(2010-01-01)
Wei, Hung-Ju
;
Meng, Chinchun
;
Su, Jen-Yi
;
Yu, Sheng-Wen
;
Huang, Guo-Wei
A 17-GHz Gilbert single-quadrature down-converter (SQDC) with polyphase filters is successfully demonstrated using 0.15-mu m pseudomorphic high electron mobility transistor (pHEMT) technology for the first time to the best of our knowledge. Thanks to the semi-insulating GaAs substrate and an advanced technology, the image rejection Gilbert mixer works well at high frequencies. A polyphase filter at the LO stage is employed to generate precisely differential quadrature signals and a four-stage polyphase filter at the IF stage can filter out the unwanted image signal to achieve image rejection. From 10-MHz to 90-MHz IF frequencies, a 30-dB image rejection ratio is achieved when RF and LO frequencies are designed around 17 GHz. The Gilbert SQDC has a 5.5-dB conversion gain, 0-dBm IP1db, and 16-dBm IIP3.
.2.4 GHz divide-by-256 similar to 271 single-ended frequency divider in standard 0.35-mu m CMOS technology
(2005)
Tseng, Sheng-Che
;
Meng, Chinchun
;
Li, Shao-Yu
;
Su, Jen-Yi
;
Huang, Guo-Wei
This paper demonstrates a low-cost 2.4 GHz single-ended frequency divider with the divide-by-value from 256 to 271 in standard 0.35-um 2P4M CMOS technology. This frequency divider is composed of a synchronous CML divide-by4/5 prescaler, an asynchronous TSPC TFF divide-by-64 divider and digital control circuitry. This proposed divider is single-ended and compatible to the single-ended low-phase-noise Colpitts VCO. The operating frequency range of the divider is from 400 MHz to 2.9 GHz. Most of input sensitivity levels are about -10 dBm and the lowest level is -25 dBm at 2.4 GHz. Its core power consumption is about 28 mW. The chip size is 1.20.7 mm(2).
40-GHz CMOS Subharmonic Gilbert Mixer With Quadrature Injection-Locked Frequency Divider
(2008)
Su, Jen-Yi
;
Meng, Chinchun
;
Wu, Po-Yi
;
Huang, Guo-Wei
;
電信工程研究所
A physics-based transit time model for GaInP/GaAs HBT devices
(2005)
Tseng, Sheng-Che
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Meng, Chinchun
;
Chen, Wei-Yu
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Su, Jen-Yi
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電信工程研究所
A compact physics-based transit time model has been established for the GaInP/GaAs HBT device. The VBIC model fails to describe the transit time frequency versus bias (I(C), V(CE)) especially at low and medium current regimes. Starting with the HICUM model, we introduce a new time constant to describe the transit time frequency versus bias (I(C), V(CE)) more precisely. This model has obvious advantage over the VBIC model to show the relation between the f(t) versus bias (I(C), V(CE)) in the low and medium current regimes for GaInP/GaAs HBT devices.
Compact CPW-MS-CPW two-stage pHEMT amplifier compatible with flip chip technique in V-band frequencies
(2008-02-01)
Su, Jen-Yi
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Meng, Chinchun
;
Lee, Yueh-Ting
;
Huang, Guo-Wei
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電信工程研究所
The V-band coplanar waveguide (CPW)-microstrip line (MS)-CPW two-stage amplifier with the flip-chip bonding technique is demonstrated using 0.15 mu m AlGaAs/InGaAs pseudomorphic high electron mobility transistor technology. The CPW is used at input and output ports for flip-chip assemblies and the MS transmission line is employed in the interstage to reduce chip size. This two-stage amplifier employs transistors as the CPW-MS transition and the MS-CPW transition in the first stage and the second stage, respectively. The CPW-MS-CPW two-stage amplifier has a gain of 14.8 dB, input return loss of 10 dB and output return loss of 22 dB at 53.5 GHz. After the flip-chip bonding, the measured performances have almost the same value.
Comparison on mHEMT Q-Band Sub-Harmonic Mixers With/Without Delay Compensation
(2010)
Syu, Jin-Siang
;
Meng, Chinchun
;
Su, Jen-Yi
;
Huang, Guo-Wei
;
電子工程學系及電子研究所
Q-band sub-harmonic mixers (SHMs) with and without delay compensation are demonstrated in this paper using 0.15-mu m metamorphic high electron mobility transistor (mHEMT) technology. A conventional stacked-LO sub-harmonic mixing cell consists of two Gilbert cells in cascode with quadrature LO inputs. The proposed compensation core in parallel with the stacked-LO core improves the port-to-port isolation. A Marchand balun is employed at the RF port to generate wideband differential signals. As a result, SHMs w/ and w/o compensation achieve the conversion gain of 1/0.5 dB and noise figure of 23/20 dB when 2f(LO)=39/42 GHz. However, the compensation circuit improves the 2LO-to-RF isolation by 12 dB, 2LO-to-IF isolation by 5 dB and RF-to-IF isolation by 5 dB without additional power consumption.
Ka/Ku-Band pHEMT Gilbert Mixers With Polyphase and Coupled-Line Quadrature Generators
(2009-05-01)
Su, Jen-Yi
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Tseng, Sheng-Che
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Meng, Chinchun
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Wu, Po-Yi
;
Lee, Yueh-Ting
In this paper, three kinds of Ka/Ku-band Gilbert mixers are demonstrated using 0.15-mu m AlGaAs/InGaAs pseudomorphic high electron mobility transistor technology. Thanks to the semiinsulating GaAs substrate, microwave passive components have a low-loss feature, and polyphase filters work up to higher frequencies. Highly accurate tantalum-nitride thin-film resistors utilized in polyphase filters result in perfect quadrature operation. Therefore, our proposed single-sideband up-converter operates at 15 GHz with a 63-dB sideband rejection ratio, and another 34-GHz in-phase/quadrature (I/Q) subharmonic down-converter reaches <0.4-dB magnitude and < 1 degrees phase errors. More than 50-dB local oscillator (LO) leakage suppression is achieved in the I/Q subharmonic mixer. On the other hand, a 40-GHz stacked-LO subharmonic mixer with a novel compensation technique is also proposed and demonstrated to improve LO speed and reduce the amount of transistors, as compared to previous work.
KU-BAND SiGe HBT I/Q SUBHARMONIC MIXER WITH REACTIVE QUADRATURE GENERATORS
(2010-07-01)
Tseng, Sheng-Che
;
Syu, Jin-Siang
;
Su, Jen-Yi
;
Wei, Hung-Ju
;
Meng, Chinchun
This article demonstrates a high-frequency 0.35-mu m SiGe HBT subharmonic downconverter with reactive in-phase and quadrature-phase (I/Q) generators. Two reactive I/Q generators are integrated in our work to provide differential quadrature RF and LO signal. The I/Q subharmonic downconverter with single-ended LO. RF. and IF (I/Q) ports has a conversion gain of 1 a. IP(1dB) of -10 dBm. IIP(3) of 0 dBm, and IIP(2) of 21 dBm at 16.4 GHz. The magnitude and phase errors between the I and Q channels are 1.34% and 0.6 degrees. respectively. The dc power consumption of this IIQ mixer without output buffers is approximately 5 mW. (C) 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1516-1520, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25281
Q-Band pHEMT and mHEMT Subharmonic Gilbert Upconversion Mixers
(2009-06-01)
Su, Jen-Yi
;
Meng, Chinchun
;
Wu, Po-Yi
;
電信工程研究所
;
Institute of Communications Engineering
This letter makes a comparison between Q-band 0.15 mu m pseudomorphic high electron mobility transistor (pHEMT) and metamorphic high electron mobility transistor (mHEMT) stacked-LO subharmonic upconversion mixers in terms of gain, isolation and linearity. In general, a 0.15 mu m mHEMT device has a higher transconductance and cutoff frequency than a 0.15 mu m pHEMT does. Thus, the conversion gain of the mHEMT is higher than that of the pHEMT in the active Gilbert mixer design. The Q-band stacked-LO subharmonic upconversion mixers using the pHEMT and mHEMT technologies have conversion gain of -7.1 dB and -0.2 dB, respectively. The pHEMT upconversion mixer has an OIP(3) of -12 dBm and an OP(1 dB) of -24 dBm, while the mHEMT one shows a 4 dB improvement on linearity for the difference between the OIP(3) and OP(1 dB). Both the chip sizes are the same at 1.3 mm x 0.9 mm.
Single-ended frequency divider with moduli of 256-271
(2006-10-01)
Tseng, Sheng-Che
;
Meng, Chinchun
;
Li, Shao-Yu
;
Su, Jen-Yi
;
Huang, Guo-Wei
This paper demonstrates a low-cost 2.4 GHz single-ended frequency divider with the divide-by-value from 256 to 271 in the standard 0.35-mu m 2P4M CMOS technology. This frequency divider is composed of a synchronous current mode logic divide-by-4/5 prescaler, an asynchronous true single-phase-clock toggle flip-flops divide-by-64 divider, and a digital control circuitry. This proposed divider is single-ended and compatible to the single-ended low-phase-noise Colpitts VCO. The operating frequency range of the divider is from 400 to 2.9 GHz. Most of the input sensitivity levels are about -10 dBm and the lowest level is -25 dBm at 2.4 GHz. Its core power consumption is about 28 mW. The chip size is 1.2 X 0.7 mm(2). (C) 2006 Wiley Periodicals, Inc.
V-band Flip-Chip pHEMT Balanced Power Amplifier with CPWG-MS-CPWG Topology and CPWG Lange Couplers
(2017-01-01)
Chang, Wei-Ling
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Su, Jen-Yi
;
Meng, Chinchun
;
Chang, Chia-Hung
;
Huang, Guo-Wei
A V-band balanced two-stage power amplifier MMICs with Lange couplers is demonstrated using 0.15 mu m GaAs pHEMT technology in this paper. A CPWG-MS-CPWG topology with via holes at the transistors as the transition between coplanar waveguide with backside ground (CPWG) and microstrip (MS) is employed for the two-stage amplifier. CPWG is applied to realize the flip-chip transition interface for both input and output ports of the amplifier and inter-stage MS matching has the advantage of small size. The structure parameters of the CPWG Lange coupler and matching network are designed and optimized for power combining. Finally, a 60-GHz balanced two-stage power amplifier using a CPWG-MS-CPWG structure delivers the small signal gain of 18 dB, OP1dB of 12 dBm and P-sat of 15 dBm.