Browsing by Author "Su, Ke-Wei"

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Investigation of anomalous inversion C-V characteristics for long-channel MOSFETs with leaky dielectrics: Mechanisms and reconstruction
(2008-02-01)
Lee, Wei
;
Su, Pin
;
Su, Ke-Wei
;
Chiang, Chung-Shi
;
Liu, Sally
This paper investigates anomalous inversion capacitance-voltage (C-V) attenuation for MOSFETs with leaky dielectrics. We propose to reconstruct the inversion C-V characteristic based on long-channel MOSFETs using the concept of intrinsic input resistance (R-ii). The concept of R-ii has been validated by segmented BSIM4/SPICE simulation. Our reconstructed C-V characteristics show poly-depletion effects, which are not visible in the two-frequency three-element method and agree well with the North Carolina State University-CVC simulation results. The intrinsic input resistance dominates the overall gate-current-induced debiasing effect (similar to 95% for L = 20 mu m) and can be extracted directly from the I-V characteristics. Due to its simplicity, our proposed R-ii approach may provide an option for regular process monitoring purposes.
Investigation of inversion capacitance-voltage reconstruction for metal oxide semiconductor field effect transistors with leaky dielectrics using BSIM4/SPICE and intrinsic input resistance model
(2007-04-01)
Lee, Wei
;
Su, Pin
;
Su, Ke-Wei
;
Chiang, Chung-Shi
;
Liu, Sally
This paper presents an inversion capacitance-voltage (C-V) reconstruction method for long-channel metal oxide semiconductor field effect transistors (MOSFETs) using the BSIM4/SPICE and the intrinsic input resistance (R-ii) model. The concept of Rii has been validated by segmented BSIM4/SPICE simulation. Since the Rii model is scalable with V-Gs and L, our R-ii approach is physically accurate. Due to its simplicity, this method may provide an option for regular process monitoring purposes.
Modeling the well-edge proximity effect in highly scaled MOSFETs
(2006-11-01)
Sheu, Yi-Ming
;
Su, Ke-Wei
;
Tian, Shiyang
;
Yang, Sheng-Jier
;
Wang, Chih-Chiang
The well-edge proximity effect caused by ion scattering during implantation in highly scaled CMOS technology is explored from a physics and process perspective. Technology computer-aided design (TCAD) simulations together with silicon wafer experiments have been conducted to investigate the impact of this effect. The ion scattering model and TCAD simulations provided a physical understanding of how the internal changes of the MOSFETs are formed. A new compact model for SPICE is proposed using physics-based understanding and has been calibrated using experimental silicon test sets.