Browsing by Author "Su, Pin"

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A Closed-Form Quantum "Dark Space" Model for Predicting the Electrostatic Integrity of Germanium MOSFETs With High-k Gate Dielectric
(2012-03-01)
Wu, Yu-Sheng
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Su, Pin
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper provides a closed-form model of the "dark space (DS)" for Ge MOSFETs with high-k gate dielectrics. This model shows accurate dependences on barrier height, surface electric field, and quantization effective mass of the channel and gate dielectric. Our model predicts that the surface DS due to quantum confinement decreases with reverse substrate bias and increasing channel doping. Our model can be also used for devices with a steep retrograde doping profile. This physically accurate model will be crucial to the prediction of the subthreshold swing and electrostatic integrity of advanced Ge devices.
A Compact Subthreshold Model for Short-Channel Monolayer Transition Metal Dichalcogenide Field-Effect Transistors
(2016-07)
You, Wei-Xiang
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Su, Pin
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This brief presents a compact subthreshold model for short-channel monolayer transition metal dichalcogenide (TMD) field-effect transistors. In this model, the impact of fringe fields from the high-K gate dielectric is considered and incorporated into a new characteristic-length expression using a single model parameter. This model has been verified with 2-D numerical simulations for TMD devices with gate length down to 5.9 nm based on ITRS 2028 low-power technology node.
A Comparative Study of Carrier Transport for Overlapped and Nonoverlapped Multiple-Gate SOI MOSFETs
(2009-07-01)
Lee, Wei
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Su, Pin
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper provides a comparative study of carrier transport characteristics for multiple-gate silicon-on-insulator MOSFETs with and without the nonoverlapped source/drain structure. For the overlapped devices, we observed Boltzmann law in subthreshold characteristics and phonon-limited behavior in the inversion regime. For the nonoverlapped devices, however, we found insensitive temperature dependence for drain current in both subthreshold and inversion regimes. Our low-temperature measurements indicate that the intersubband scattering is the dominant carrier transport mechanism for narrow overlapped multigate field-effect transistors (MuGFETs). For the nonoverlapped MuGFETs, the voltage-controlled potential barriers in the nonoverlapped regions may give rise to the weak localization effect (conductance reduction) and the quantum interference fluctuations.
A Comprehensive Comparative Analysis of FinFET and Trigate Device, SRAM and Logic Circuits
(2012)
Pao, Chia-Hao
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Fan, Ming-Long
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Tsai, Ming-Fu
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Chen, Yin-Nien
;
Hu, Vita Pi-Ho
We present a comprehensive comparative analysis of FinFET and Trigate device characteristics, 6T SRAM stability and logic circuits. The impact of intrinsic random device variations, including fin Line Edge Roughness (LER), Work Function Variation (WFV) and fin width scaling on FinFET and Trigate device Subthreshold Slope (S. S.), V-T, 6T SRAM Read Static Noise Margin (RSNM) and Write Static Noise Margin (WSNM) are investigated and compared by using 3D atomistic TCAD simulation. The results indicate that Trigate device shows slightly better variability control under the same electrical width and fin width (10nm and 7nm) considering fin LER and WFV. Next, we investigate the impact of single charged trap induced Random Telegraph Noise (RTN) on FinFET and Trigate device characteristics, 6T SRAM and logic circuits. The top-gate and the lower fin height of Trigate device under the same electrical width and fin width cause the current density to concentrate close to the bottom of the fin, resulting in stronger dependence on the location of the trap, larger RTN Delta I-D/I-D amplitude and larger Delta V-T with a trap placed at the worst position under fin LER and WFV. The impact of RTN trapping/detrapping on 6T SRAM RSNM, the leakage-delay of inverter, Two-Way NAND and 2-To-1 Multiplexer (MUX) are examined. With degreasing supply voltage, the RTN degradation of Trigate SRAM RSNM and logic circuits become larger compared with the FinFET counterparts.
A Comprehensive Investigation of Analog Performance for Uniaxial Strained PMOSFETs
(2009-02-01)
Kuo, Jack Jyun-Yan
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Chen, William Po-Nien
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Su, Pin
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents a comprehensive investigation of the analog performance for uniaxial strained PMOSFETs with sub-100 nm gate length. Through a comparison between co-processed strained and unstrained devices regarding important analog metrics such as transconductance to drain current ratio (g(m)/I(d)), dc gain, linearity, low-frequency noise, and device mismatch, the impact of process-induced uniaxial strain on the analog performance of MOS devices has been assessed and analyzed. Our results indicate that, although the drain current noise spectral density and drain current mismatch of the strained device under low gate voltage overdrive are increased because of the larger gate-bias sensitivity of carrier mobility, the strained device has almost the same low frequency and mismatch performance as the unstrained one at a given g(m)/I(d). This paper may provide insights for analog design using advanced strained devices.
A Comprehensive Kinetical Modeling of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Energy Effects on Negative Capacitance FETs
(2019-01-01)
Tang, Y-T
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Fang, C-L
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Kao, Y-C
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Modolo, N.
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Su, C-J
This paper clarifies for the first time the origin of ferroelectricity in the Negative Capacitance Field-Effect Transistors (NCFETs) by molecular dynamics (MD) simulation. MD simulation considering atomic interactions between all atoms enables accurate predictions for the microstructure even at all interfaces. By incorporating the results from MD simulations into a kinetic model, it is able to predict the conditions of crystallization and phase transition during RTP and cooling processes that govern ferroelectricity in FETs. Our simulation reveals that the comparable interfacial energy between o- and t- phase, and in-plane tensile stress from metal capping or interfacial layers (ILs) enable more phase transition from t- to o-phase, and more ferroelectricity in NCFETs. Finally, design methodology to maintain the electric variation of NCFETs is also proposed
A Comprehensive Study of Single-Electron Effects in Multiple-Gate MOSFETs
(2008)
Lee, Wei
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Su, Pin
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A New 8T Hybrid Nonvolatile SRAM With Ferroelectric FET
(2020-01-01)
You, Wei-Xiang
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Su, Pin
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Hu, Chenming
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電子工程學系及電子研究所
;
國際半導體學院
This paper proposes a new 8T nonvolatile SRAM (nvSRAM) cell employing ULP FinFETs and ferroelectric FinFETs to enable energy-efficient and low-latency store/recall operations. Different from other types of nvSRAM requiring additional circuitry or nonvolatile memories connected to a standard 6T SRAM cell to achieve nonvolatility, the proposed hybrid nvSRAM cell reduces the area penalty by embedding the nonvolatile ferroelectric FinFETs in a 6T SRAM cell without sacrificing the cell stability, read/write performance and power consumption.
A New and Simple DC Method for Thermal-Resistance Extraction of Scaled FinFET Devices
(2018-01-01)
Huang, Wei-Cheng
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Su, Pin
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work proposes a new and simple hot-chuck measurement method for the extraction of the thermal resistance of FinFETs. The intrinsic transconductance that eliminates the parasitic source/drain resistance effect can serve as a temperature sensor to characterize the device temperature rise due to self-heating. Our method requires only DC measurements without the need of special test structures.
Accurate modeling and characterization of mobility in tensile and compressive stress for state-of-the-art manufacturing NMOSFETs
(2007)
Wang, J. -S.
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Chen, William P. N.
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Shih, C. -H.
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Lien, C.
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Su, Pin
Analysis of GeOI FinFET 6T SRAM Cells With Variation-Tolerant WLUD Read-Assist and TVC Write-Assist
(2015-06-01)
Hu, Vita Pi-Ho
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Fan, Ming-Long
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Su, Pin
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Chuang, Ching-Te
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電子工程學系及電子研究所
This paper analyzes the impacts of read-assist and write-assist circuits on GeOI FinFET 6T SRAM cells considering intrinsic random variations, process corner, and temperature variation. The word-line under-drive (WLUD) read-assist is more efficient to improve the read static noise margin and read V-MIN of fast-N slow-P corner GeOI FinFET SRAM cells compared with the Silicon-On-Insulator (SOI) counterparts. GeOI FinFET SRAM cells with WLUD show less cell read access-time degradation compared with the SOI counterparts at both 25 degrees C and 125 degrees C. With transient voltage collapse (TVC) write-assist, the write-ability and variation tolerance of GeOI and SOI FinFET SRAM cells are improved. The temperature dependence of data retention time is different between the GeOI and SOI FinFET SRAM cells. The maximum TVC write-assist pulsewidth constrained by the data retention failure is smaller in GeOI FinFET SRAMs at 25 degrees C and becomes comparable at 125 degrees C compared with the SOI FinFET SRAMs.
Analysis of Germanium FinFET Logic Circuits and SRAMs with Asymmetric Gate to Source/Drain Underlap Devices
(2013)
Hu, Vita Pi-Ho
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Fan, Ming-Long
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Su, Pin
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Chuang, Ching-Te
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電子工程學系及電子研究所
Analysis of Germanium FinFET on SOI substrate (GeOI FinFET) at device and circuit level is presented. The amplified Band-To-Band Tunneling (BTBT) leakage of GeOI FinFETs is observed due to the parasitic bipolar effect, and the BTBT induced parasitic bipolar leakage dominates the leakage current of GeOI FinFET. The effectiveness of different dual-Vt technology options including increasing channel doping, increasing gate length and drain-side underlap for leakage reduction is analyzed for GeOI FinFET logic circuits and SRAMs. Drain-side underlap is the most effective way for leakage reduction of GeOI FinFETs, while increasing channel doping is the least effective way for leakage reduction of GeOI FinFETs. An optimum asymmetric underlap design in SRAM using asymmetric underlap pull-up and access transistors (PUAX-asym) is proposed. GeOI FinFETs with asymmetric underlap design show significant improvement in leakage-delay performance and stability in logic circuits and SRAM cells.
Analysis of Single-Trap-Induced Random Telegraph Noise and its Interaction With Work Function Variation for Tunnel FET
(2013-06-01)
Fan, Ming-Long
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Hu, Vita Pi-Ho
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Chen, Yin-Nein
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Su, Pin
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Chuang, Ching-Te
This paper analyzes the impacts of a single acceptor-type and donor-type interface trap induced random telegraph noise (RTN) on tunnel FET (TFET) devices and its interaction with work function variation (WFV) using atomistic 3-D TCAD simulations. Significant RTN amplitude (Delta I-D/I-D) is observed for a single acceptor trap near the tunneling junction, whereas a donor trap is found to cause more severe impact over a broader region across the channel region. In addition, several device design parameters that can be used to improve TFET subthreshold characteristics (thinner equivalent oxide thickness or longer L-eff) are found to increase the susceptibility to RTN. Our results indicate that under WFV, TFET exhibits weaker correlation between I-ON and I-OFF than that in the conventional MOSFET counterpart. In the presence of WFV, the RTN amplitude can be enhanced or reduced depending on the type of the trap and the composition/orientation of metal-gate grain.
Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits
(2012-08-01)
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Chen, Yin-Nien
;
Su, Pin
;
Chuang, Ching-Te
This paper analyzes the impacts of single-charged-trap-induced random telegraph noise (RTN) on FinFET devices in tied- and independent-gate modes, 6T static random access memory (SRAM) cell stability, and several basic logic circuits. The dependence of RTN on trap location, EOT, and temperature is evaluated through 3-D atomistic TCAD simulation. It is observed that the charged trap located near the bottom of sidewall (gate) interface and in the middle region between the source and drain will result in the most significant impact. EOT scaling and higher operating temperature improve the immunity to RTN. RTN degradation in independent-gate mode and the dependence on the location of the trap and bias-dependent current-conduction path are analyzed. We show that the planar BULK device, with larger subthreshold swing (S.S.) and comparable trap-induced V-T shift, exhibits less nominal RTN degradation than FinFET for traps placed in the worst position. However, the larger variability and surface conduction characteristic of the planar BULK device lead to broader dispersion and larger worst case RTN degradation than the FinFET device with smaller variability and volume conduction. For traps randomly placed across the interface, similar RTN amplitude dispersions are observed for FinFET and planar BULK devices except in the vicinity of distribution tail due to the strong interaction between the charged trap and discrete random dopants in planar BULK devices. For 6T FinFET SRAM cell, the READ static noise margin of 64 possible combinations from trapping/detrapping in each cell transistor is examined. Because of reduced carriers with decreasing supply voltage (V-dd), the importance of RTN on subthreshold cell stability increases. Moreover, the leakage and delay of FinFET inverters, two-way NAND, and two-to-one multiplexer are investigated using 3-D TCAD mixed-mode simulations. The RTN is found to cause similar to 24%-27% and similar to 13%-15% variations in leakage and delay at V-dd = 0.4 V, respectively, for the logic circuits evaluated.
"Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits"
(2012-08-01)
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Chen, Yin-Nien
;
Su, Pin
;
Chuang, Ching-Te
"This paper analyzes the impacts of single-charged-trap-induced random telegraph noise (RTN) on FinFET devices in tied- and independent-gate modes, 6T static random access memory (SRAM) cell stability, and several basic logic circuits. The dependence of RTN on trap location, EOT, and temperature is evaluated through 3-D atomistic TCAD simulation. It is observed that the charged trap located near the bottom of sidewall (gate) interface and in the middle region between the source and drain will result in the most significant impact. EOT scaling and higher operating temperature improve the immunity to RTN. RTN degradation in independent-gate mode and the dependence on the location of the trap and bias-dependent current-conduction path are analyzed. We show that the planar BULK device, with larger subthreshold swing (S.S.) and comparable trap-induced V-T shift, exhibits less nominal RTN degradation than FinFET for traps placed in the worst position. However, the larger variability and surface conduction characteristic of the planar BULK device lead to broader dispersion and larger worst case RTN degradation than the FinFET device with smaller variability and volume conduction. For traps randomly placed across the interface, similar RTN amplitude dispersions are observed for FinFET and planar BULK devices except in the vicinity of distribution tail due to the strong interaction between the charged trap and discrete random dopants in planar BULK devices. For 6T FinFET SRAM cell, the READ static noise margin of 64 possible combinations from trapping/detrapping in each cell transistor is examined. Because of reduced carriers with decreasing supply voltage (V-dd), the importance of RTN on subthreshold cell stability increases. Moreover, the leakage and delay of FinFET inverters, two-way NAND, and two-to-one multiplexer are investigated using 3-D TCAD mixed-mode simulations. The RTN is found to cause similar to 24%-27% and similar to 13%-15% variations in leakage and delay at V-dd = 0.4 V, respectively, for the logic circuits evaluated."
Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity
(2011-09-01)
Hu, Vita Pi-Ho
;
Fan, Ming-Long
;
Su, Pin
;
Chuang, Ching-Te
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電子工程學系及電子研究所
This paper analyzes stability and variability of ultrathin-body (UTB) SOI subthreshold SRAMs considering line- edge roughness (LER), work function variation (WFV), and temperature sensitivity. The intrinsic advantages of UTB SOI technology versus bulk CMOS technology with regard to the stability and variability of 6T SRAM cells for subthreshold operation are analyzed. Compared with LER, WFV causes comparable threshold voltage variation and much smaller subthreshold swing fluctuation, hence less impact on the UTB SOI subthreshold SRAMs. Even considering LER, the Lg = 40 nm UTB SOI 6T subthreshold SRAM cells still provide sufficient margin (mu RSNM/sigma RSNM > 6 at Vdd = 0.3 similar to 0.4 V) while the bulk subthreshold SRAMs with RDF fail to maintain adequate margin. Increasing temperature will increase the Vread,0 and decrease RSNM because of the degraded subthreshold swing. The RSNM of UTB SOI subthreshold SRAMs showless temperature sensitivity compared with that of bulk subthreshold SRAMs. Due to larger body effect, the back-gating technique is more efficient for the Lg = 40 nm and 25 nm UTB SOI subthreshold SRAMs compared with the bulk counterparts. By using lower threshold voltage devices with dual band-gapwork functions, the Lg = 25 nm UTB SOI subthreshold SRAMs show 31.9% reduction in sigma RSNM and 55% improvement in mu RSNM/sigma RSNM.
Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity
(2011-09-01)
Hu, Vita Pi-Ho
;
Fan, Ming-Long
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
This paper analyzes stability and variability of ultrathin-body (UTB) SOI subthreshold SRAMs considering line- edge roughness (LER), work function variation (WFV), and temperature sensitivity. The intrinsic advantages of UTB SOI technology versus bulk CMOS technology with regard to the stability and variability of 6T SRAM cells for subthreshold operation are analyzed. Compared with LER, WFV causes comparable threshold voltage variation and much smaller subthreshold swing fluctuation, hence less impact on the UTB SOI subthreshold SRAMs. Even considering LER, the Lg = 40 nm UTB SOI 6T subthreshold SRAM cells still provide sufficient margin (mu RSNM/sigma RSNM > 6 at Vdd = 0.3 similar to 0.4 V) while the bulk subthreshold SRAMs with RDF fail to maintain adequate margin. Increasing temperature will increase the Vread,0 and decrease RSNM because of the degraded subthreshold swing. The RSNM of UTB SOI subthreshold SRAMs showless temperature sensitivity compared with that of bulk subthreshold SRAMs. Due to larger body effect, the back-gating technique is more efficient for the Lg = 40 nm and 25 nm UTB SOI subthreshold SRAMs compared with the bulk counterparts. By using lower threshold voltage devices with dual band-gapwork functions, the Lg = 25 nm UTB SOI subthreshold SRAMs show 31.9% reduction in sigma RSNM and 55% improvement in mu RSNM/sigma RSNM.
Analytical Quantum-Confinement Model for Short-Channel Gate-All-Around MOSFETs Under Subthreshold Region
(2009-11-01)
Wu, Yu-Sheng
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Su, Pin
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents an analytical model for quantum-confinement effects in short-channel gate-all-around (GAA) MOSFETs under the subthreshold region. Our analytical model accurately predicts the impact of short-channel effects and doping concentration on the quantum-confinement effects. This scalable quantum-confinement model is crucial to the ultrascaled GAA MOSFET design.
Anomalous Electrostatics and Intrinsic Variability in GeOI p-MOSFET
(2014)
Yu, Chang-Hung
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Su, Pin
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
We have reported anomalous electrostatic behaviors in drain-induced-barrier-lowering (DIBL), threshold voltage (VT) roll-off, subthreshold swing (SS), and intrinsic VT variability in GeOI p-MOSFET. The underlying mechanism responsible for these anomalous electrostatic characteristics is attributed to the valence-band offset between Ge channel and Si substrate due to their significant discrepancy in bandgap. This band offset results in an effective built-in forward body bias in GeOI pFET, and leads to different carrier profiles between GeOI pFET and nFET.
Band-to-Band-Tunneling Leakage Suppression for Ultra-Thin-Body GeOI MOSFETs Using Transistor Stacking
(2012-02-01)
Hu, Vita Pi-Ho
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Fan, Ming-Long
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Su, Pin
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Chuang, Ching-Te
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電子工程學系及電子研究所
This letter indicates that the ultra-thin-body (UTB) germanium-on-insulator (GeOI) MOSFETs preserve the leakage reduction property of stacking devices, while the band-to-band-tunneling leakage of bulk Ge-channel devices cannot be reduced by stacking transistors. The seemingly contradictory behavior of the stack-effect factors is explained by the difference in the flows of band-to-band-tunneling hole fluxes for UTB GeOI and bulk Ge-channel devices and validated by TCAD mixed-mode simulations. At 300 K, the stack-effect factors of UTB GeOI MOSFETs range from 6.8 to 40 (N = 2) and from 12 to 142 (N = 3) at Vdd = 0.5-1V. As the temperature increases or Vdd decreases, the stack-effect factor for UTB GeOI devices decreases, while the stack-effect factor for bulk Ge-channel MOSFETs increases, because the subthreshold leakage current becomes more significant at higher temperature or lower voltage with respect to the band-to-band-tunneling leakage current.