Browsing by Author "Su, Po-Cheng"

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A Numerical Study of Si-TMD Contact with n/p Type Operation and Interface Barrier Reduction for Sub-5 nm Monolayer MoS2 FET
(2016-01-01)
Tang, Ying-Tsan
;
Li, Kai-Shin
;
Li, Lain-Jong
;
Li, Ming-Yang
;
Lin, Chang-Hsien
An atomic-scale numerical study of Si contact with transition metal dichalcogenides (TMD) semiconductor materials is proposed by first-principles simulation for the first time. The monolayer MoS2 channel can be operated as both of n- and p-type FET by properly doping Si S/D to adjust the TMD channel potential. The gradient MoSx junction of dichalcogenide vacancies enables Si-MoS2 contact resistance lower than 100 Omega-mu m for interface Schottky barrier height reduction. The compact Si-MoS2 interface study can potentially provide monolayer TMD contact design guideline for the sub-5 nm TMD FET fabrication technology.
Analytical Modeling of Read-Induced SET-State Conductance Change in a Hafnium-Oxide Resistive Switching Device
(2020-01-01)
Su, Po-Cheng
;
Jiang, Cheng-Min
;
Chen, Yu-Jia
;
Wang, Chih-Chieh
;
Li, Kai-Shin
A SET-state conductance change in a hafnium-oxide resistive switching memory cell due to repeated read events is investigated. We characterize a read-induced conductance change at different read voltages and SET-state conductance levels. Our result shows that the read-induced conductance degradation exhibits a two-stage evolution with the read pulse number. A SET-state conductance decreases slightly in the first stage and then follows inverse power-law dependence on the read number in the second stage. The power factor is an exponential function of a read voltage without regard to the SET-state conductance level, and the read pulse number at the transition of the two stages is related to a read voltage and conductance level. An analytical model to describe the two-stage conductance evolution is proposed. The parameters in the model are extracted from measurement data. Our model is verified by good agreement between the modeled and measured results in a wide range of read pulse number, read voltage, and SET-state conductance level.
Characterization and modeling of SET/RESET cycling induced read-disturb failure time degradation in a resistive switching memory
(2017-12-07)
Su, Po-Cheng
;
Hsu, Chun-Chi
;
Du, Sin-I
;
Wang, Tahui
;
電機學院
Read operation induced disturbance in SET-state in a tungsten oxide resistive switching memory is investigated. We observe that the reduction of oxygen vacancy density during read-disturb follows power-law dependence on cumulative read-disturb time. Our study shows that the SET-state read-disturb immunity progressively degrades by orders of magnitude as SET/RESET cycle number increases. To explore the cause of the read-disturb degradation, we perform a constant voltage stress to emulate high-field stress effects in SET/RESET cycling. We find that the read-disturb failure time degradation is attributed to high-field stress-generated oxide traps. Since the stress-generated traps may substitute for some of oxygen vacancies in forming conductive percolation paths in a switching dielectric, a stressed cell has a reduced oxygen vacancy density in SET-state, which in turn results in a shorter read-disturb failure time. We develop an analytical read-disturb degradation model including both cycling induced oxide trap creation and read-disturb induced oxygen vacancy reduction. Our model can well reproduce the measured read-disturb failure time degradation in a cycled cell without using fitting parameters. Published by AIP Publishing.
Cycling-Induced SET-Disturb Failure Time Degradation in a Resistive Switching Memory
(2015-02-01)
Chung, Yueh-Ting
;
Su, Po-Cheng
;
Cheng, Yu-Hsuan
;
Wang, Tahui
;
Chen, Min-Cheng
A new degradation mode with respect to write-disturb failure time due to SET/RESET cycling in a tungsten oxide resistive random access memory is reported. In a crossbar array memory, we find that a write-disturb failure time in high resistance state reduces suddenly by several orders of magnitude after certain SET/RESET cycles. This abrupt degradation is believed due to the creation of a new soft breakdown path in a switching dielectric by cycling stress. Although a memory window still remains after the degradation, the occurrence probability of over-SET state increases significantly. This cycling-induced degradation mode imposes a serious constraint on the number of SET-disturb pulses and thus an endurance cycle number in a resistive switching memory.
Modeling of Read-Disturb-Induced SET-State Current Degradation in a Tungsten Oxide Resistive Switching Memory
(2018-11-01)
Su, Po-Cheng
;
Jiang, Cheng-Min
;
Wang, Chih-Wei
;
Wang, Tahui
;
電子工程學系及電子研究所
We characterize SET-state current degradation induced by read operations in a tungsten oxide resistive memory cell. The current degradation exhibits a two-stage evolution. In the second stage, the current decline follows inverse power-law dependence on cumulative read-disturb time. We present an analytical model to derive the inverse power law. Our model includes oxygen ion activation, mobile oxygen ion hopping, and the reduction of oxygen vacancy density by re-oxidation. Voltage and temperature effects on read-disturb-induced degradation are characterized for comparison with the model. Our results show that the power factor in the inverse power law has exponential dependence on a read voltage.
SET/RESET Cycling-Induced Trap Creation and SET-Disturb Failure Time Degradation in a Resistive-Switching Memory
(2016-06)
Chung, Yueh-Ting
;
Su, Po-Cheng
;
Lin, Wen-Jie
;
Chen, Min-Cheng
;
Wang, Tahui
Characterization and modeling of SET/RESET cycling-induced SET-disturb failure time degradation in a tungsten oxide resistive random access memory are performed. We find that write-disturb failure time in a high-resistance state (HRS) cell abruptly degrades by the orders of magnitude after certain SET/RESET cycles. To investigate this new degradation mode, we perform the constant voltage stress in high-resistance state (HRS) to characterize the trap generation in a switching dielectric by measuring a stress-induced leakage current and a low-frequency noise. The constant voltage stress is to emulate high-field stress and, thus, trap creation in SET/RESET cycling. We find that a low-field current in HRS by trap-assisted tunneling in a rupture region gradually increases in both the constant voltage stress and the SET/RESET cycling stress. The high-field stress-generated traps, unlike SET-induced oxygen vacancies, cannot be annihilated by RESET operation and are held responsible for a RESET endurance failure. A 3-D Monte Carlo model based on a percolation concept of oxide breakdown is developed to simulate a SET-disturb failure time. Our model includes both the stress-generated traps and the SET-disturb-induced oxygen vacancies. The model can well explain the observed abrupt and the drastic SET-disturb lifetime degradation, which is attributed to the formation of a conductive percolation path of stress-generated traps.
TMD FinFET with 4 nm Thin Body and Back Gate Control for Future Low Power Technology
(2015)
Chen, Min-Cheng
;
Li, Kai-Shin
;
Li, Lain-Jong
;
Lu, Ang-Yu
;
Li, Ming-Yang
A 4 nm thin transition-metal dichalcogenide (TMD) body FinFET with back gate control is proposed and demonstrated for the first time. The TMD FinFET channel is deposited by CVD. Hydrogen plasma treatment of TMD is employed to lower the series resistance for the first time. The 2 nm thin back gate oxide enables 0.5 V of Vth shift with 1.2 V change in back bias for correcting device variations and dynamically configuring a device as a high performance or low leakage device. TMD can potentially provide sub-nm thin monolayer body needed for 2 nm node FinFET.