Browsing by Author "Su, Yi-Ping"

Now showing 1 - 20 of 27

0.65V-Input-Voltage 0.6V-Output-Voltage 30ppm/degrees C Low-Dropout Regulator with Embedded Voltage Reference for Low-Power Biomedical Systems
(2014-01-01)
Chen, Wei-Chung
;
Su, Yi-Ping
;
Lee, Yu-Huei
;
Wey, Chin-Long
;
Chen, Ke-Horng
200nA Low Quiescent Current Deep-Standby Mode in 28nm DC-DC Buck Converter for Active Implantable Medical Devices
(2015)
Chu, Li-Cheng
;
Yang, Te-Fu
;
Huang, Ru-Yu
;
Su, Yi-Ping
;
Lin, Chiun-He
the proposed deep-standby mode (DSM) is used in 28nm power management unit (PMU) for long-term usage in active implantable medical devices (AIMD). The PMU can upgrade its normal mode with the proposed embedded auto-cancellation (EAC) technique in order to have high accuracy even if the battery is aging and the PVT variations occur. The test chip fabricated in 28nm CMOS process features low quiescent current of 200nA and output voltage accuracy of 98%. Seamless transition among the DSM and the accurate mode demonstrates both low quiescent current and high accuracy can be achieved in the proposed PMU.
90% Peak Efficiency Single-Inductor-Multiple-Output DC-DC Buck Converter with Output Independent Gate Drive Control
(2015-01-01)
Su, Yi-Ping
;
Lin, Chiun-He
;
Peng, Shen-Yu
;
Huang, Ru-Yu
;
Yang, Te-Fu
92% High Efficiency and Low Current Mismatch Interleaving Power Factor Correction Controller With Variable Sampling Slope and Automatic Loading Detection Techniques
(2013-11-01)
Su, Yi-Ping
;
Chen, Chun-Yen
;
Ni, Chia-Lung
;
Kang, Yu-Chai
;
Chen, Yi-Ting
This paper proposes the dual nondeadtime variable sampling slope technique to carry out precise phase sensing and suppress phase error in interleaving power factor correction (PFC) controller over a whole ac switching cycle for low current mismatch. Furthermore, the proposed automatic loading detection (ALD) technique can keep efficiency higher than 92% over a wide load range due to accurately controlling the ON/OFF of dual phases. The test circuit fabricated in the TSMC 0.5-mu m 800-V UHV process shows that the highly integrated interleaving PFC can deliver a high power of 180 W and a high efficiency of 95% at an output power of 180 W.
94% Performance Improvement by Time-shift Control (TSC) Technique in Cloud Computing Voltage Regulator Module (VRM)
(2013)
Meng, Che-Hao
;
Su, Yi-Ping
;
Huang, Yu-Ping
;
Lee, Yu-Huei
;
Chen, Ke-Horng
the time-shift control (TSC) technique for voltage regulator module (VRM) is proposed to achieve high performance power supply for servers in cloud computing. Four power stages are adopted to provide high current driving capability and low output ripple. Besides, the power request, which includes the number of active phases and voltage identification (VID), is acknowledged by servers for high driving capability during high throughput and high efficiency during standby mode. Furthermore, to equally distribute the current in each phase, the proposed TSC technique improves the current balance performance and solves the stability problem. In the scale-down clouding computing prototype, the efficiency can be kept higher than 90% over a wide load current range of 2 A. Besides, the performance and operating frequency of the servers in stable operation are not limited by the VRM with the TSC.
A Compact Power Management for Next Generation Intensive Care Unit with 91% Conversion Efficiency
(2014-01-01)
Chiu, Chao-Chang
;
Yang, Hsiang-An
;
Su, Yi-Ping
;
Chang, Chih-Wei
;
Meng, Che-Hao
the proposed single-inductor dual-output (SIDO) converter with energy-conservation mode (ECM) control is designed for next generation intensive care unit. The energy-conservation mode (ECM) control generates two different energy delivery paths for dual buck outputs with only one inductor. In addition, the superposition technique is used to achieve a minimized inductor current level. The average inductor current is equal to the summation of two output loads. The measurement results shows the 91% peak efficiency can he derived.
A Wide Load Range and High Efficiency Switched-Capacitor DC-DC Converter With Pseudo-Clock Controlled Load-dependent Frequency
(2014-03-01)
Chen, Wei-Chung
;
Ming, Da-Long
;
Su, Yi-Ping
;
Lee, Yu-Huei
;
Chen, Ke-Horng
A high efficiency 3.3V-to-1V switched-capacitor (SC) step-down DC-DC converter with load-dependent frequency control (LFC) and deep-green mode (DGM) operation is proposed for system-on-a-chip (SoC) application. According to output loading current, the LFC technique can immediately and dynamically adjust the switching frequency through the use of pseudo-clock generator (PCG) and lead-lag detector (LLD) circuit to obtain high power conversion efficiency and small output voltage ripple over a wide loading current range. Therefore, adequate loading current supplying function and output voltage regulation can be guaranteed. Moreover, the DGM operation, similar to pulse skipping mode, can mask the switching clock to reduce power loss at ultra-light loads for further improving power efficiency. The test chip fabricated in 55 nm CMOS process demonstrates that the proposed fast transient converter can deliver wide load range from 10 mA to 250 mA with two small flying capacitors (C-F1, C-F2 = 0.1 mu F) and one output capacitor (C-OUT = 1 mu F). The peak conversion efficiency is 89% compared to the ideal value of 91% (3 * V-OUT/V-IN). In other words, the peak normalized efficiency is equal to 98%. The overall normalized efficiency is always kept higher than 90% while the output voltage ripple is guaranteed smaller than 30 mV.
An Embedded Dynamic Voltage Scaling (DVS) System Through 55 nm Single-Inductor Dual-Output (SIDO) Switching Converter for 12-Bit Video Digital-to-Analog Converter
(2012-07-01)
Chou, Wen-Shen
;
Huang, Tzu-Chi
;
Lee, Yu-Huei
;
Yang, Yao-Yi
;
Su, Yi-Ping
"This paper proposes a 55 nm CMOS 12-bit current- steering video digital-to-analog converter (DAC) directly powered by the single-inductor dual-output (SIDO) switching converter to compose a dynamic voltage scaling (DVS) system and improve the power efficiency. Dual-DVS control in both digital and analog circuits can effectively reduce power consumption. With various supply voltages, the video DAC can meet several different specifications in the power optimized (PO) mode. Furthermore, for DAC, the proposed 3S method, including finger separating, splitting and shifting, achieves good differential nonlinearity (DNL) performance to 0.78/0.4 least significant bit (LSB) and integral nonlinearity (INL) 1.3/1.0 LSB (with/without SIDO converter) without additional calibration. It also suppresses the switching noise interference from the SIDO converter. Moreover, for SIDO converter, the cross-regulation performance is greatly improved in both transient and steady state to achieve lowest interference for the analog supply. The total power efficiency can be improved up to 11.5% and 28% in the DVS and the PO mode. The SIDO supplied DAC with the dual-DVS function achieves 69.88 dB spurious free dynamic range (SFDR) at the 1 V output swing and 1 MHz input. The proposed intrinsic 12-bit DAC and SIDO converter achieve high definition video DAC performance with the benefit of area and energy efficiency."
Automatic Loading Detection (ALD) Technique for 92% High Efficiency Interleaving Power Factor Correction (PFC) Over a Wide Output Power of 180W
(2012)
Tsai, Jen-Chive
;
Chen, Chun-Yen
;
Chen, Yi-Ting
;
Ni, Chia-Lung
;
Su, Yi-Ping
the proposed automatic loading detection (ALD) technique keeps high efficiency in interleaving power factor correction (PFC) over a wide load range. With the advantages of small input/output filter and output ripple in the interleaving mechanism, the improved efficiency by the ALD technique at light loads due to reduced switching loss can be widely used in the adapter of portable electronics. The ALD technique can calculate the power by the detection of peak input voltage to reduce the switching loss since the slave channel can be completely turned off for power saving at light loads. Therefore, the boundary control mode (BCM) control can simultaneously provide high power and keep high conversion efficiency both at light and heavy loads. The highly integrated PFC controller fabricated in TSMC 800V UHV process shows high efficiency of 92% over a wide output power of 180 W.
Automatic Power Monitor (APM) in Switching Charger with Smooth Transition Loop Selector (STLS) for High-energy Throughput System
(2012)
Tsai, Tsu-Wei
;
Peng, Ruei-Hong
;
Su, Yi-Ping
;
Chen, Ya-Ping
;
Chen, Ke-Horng
This paper proposed a switch-based charger system instead of LDO-based charger for Li-Ion batteries. The automatic power monitor (APM) controls three main power delivery paths to generate five different charging cases. Moreover, with the proposed smooth transition loop selector (STLS), the charging process can transfer smoothly and never oscillate between two consecutive stages. Furthermore, the STLS can bear different batteries with wide built-in resistance variation by adjusting charging factors. The stability analysis proves that the stability of APM loop is guaranteed by only one Type-III compensator. The simulation results ensure the performance of the system controlled by APM even if the power source is unable to provide sufficient power.
Batteryless 275mV Startup Single-Cell Photovoltaic Energy Harvesting System for Alleviating Shading Effect
(2013-01-01)
Huang, Chao-Jen
;
Su, Yi-Ping
;
Chen, Ke-Horng
;
Huang, Li-Ren
;
Chu, Fang-Chih
without any batteries, a low input voltage converter is presented for a single-cell (SC) photovoltaic (PV) energy harvesting to alleviate the energy degradation due to shading effect. The proposed low voltage startup (LVS) circuit with low input voltage of 275 mV and less than 840 ms startup time achieves high voltage conversion ratio to supply a high accuracy bandgap reference. Experimental results show the maximum power throughput is up to 6 mW and the quiescent power is less than 650 mu W with integrated two buck-boost converters and two boost converters. The peak efficiency of the boost converter can be up to 75.8% for ultra-low voltage hearing aid systems.
Batteryless 275mV Startup Single-Cell Photovoltaic Energy Harvesting System for Alleviating Shading Effect
(2013-01-01)
Huang, Chao-Jen
;
Su, Yi-Ping
;
Chen, Ke-Horng
;
Huang, Li-Ren
;
Chu, Fang-Chih
without any batteries, a low input voltage converter is presented for a single-cell (SC) photovoltaic (PV) energy harvesting to alleviate the energy degradation due to shading effect. The proposed low voltage startup (LVS) circuit with low input voltage of 275 mV and less than 840 ms startup time achieves high voltage conversion ratio to supply a high accuracy bandgap reference. Experimental results show the maximum power throughput is up to 6 mW and the quiescent power is less than 650 mu W with integrated two buck-boost converters and two boost converters. The peak efficiency of the boost converter can be up to 75.8% for ultra-low voltage hearing aid systems.
Boundary Conduction Mode Controlled Power Factor Corrector With Line Voltage Recovery and Total Harmonic Distortion Improvement Techniques
(2014-07-01)
Su, Yi-Ping
;
Ni, Chia-Lung
;
Chen, Chun-Yen
;
Chen, Yi-Ting
;
Tsai, Jen-Chieh
The proposed line voltage recovery (LVR) and the total harmonic distortion improvement (THDI) technique improve power factor (PF) and total harmonic distortion (THD) over a wide line voltage range in boundary conduction mode controlled power factor corrector (PFC). The LVR detects the input line root-mean-square voltage to generate the digital equivalent code to the THDI for optimizing the THD by tuning the on-time value at different line voltages. In addition, the LVR and the THDI provide a feedforward path to reduce the ripple of the feedback voltage for further improving the THD. Therefore, the PFC controller can keep high PF and low THD over a wide line voltage. Experimental results demonstrate that the peak PF value is 0.998 and the minimum THD is 1.7% by the test circuit fabricated in a TSMC 800-V ultrahigh-voltage process with the universal line voltage range of 90-264 V.
CCM/GM Relative Skip Energy Control and Bidirectional Dynamic Slope Compensation in a Single-Inductor Multiple-Output DC-DC Converter for Wearable Device Power Solution
(2016-08)
Su, Yi-Ping
;
Lin, Chiun-He
;
Yang, Te-Fu
;
Huang, Ru-Yu
;
Chen, Wei-Chung
Compact size wearable devices require multiple supplies with relative large loading difference, which causes serious cross regulation, large ripple, and oscillation in single-inductor multiple-output (SIMO) DC-DC converter. Thus, a continuous conduction mode/green mode (CCM/GM) relative skip energy control (RSEC) in SIMO is proposed for wearable device power solution. Different from the conventional absolute skip method, the RSEC eliminates unnecessary skip-induced voltage ripple and cross regulation with well regulation performance over wide load and voltage ranges. Optimization between efficiency and voltage ripple achieves low noise supply and reduced switching loss. In addition, smooth transition between CCM and GM provides high power and longer usage time in wearable devices. Furthermore, bidirectional dynamic slope compensation conquers subharmonic oscillation and avoids invalid pulses in the energy delivery operation of current-mode SIMO DC-DC converters. The test chip fabricated in the 0.18 mu m CMOS process occupies 2.24 mm(2) active area. Maximum output ripple, overshoot/undershoot, and cross regulation are kept below 40 mV, 27 mV, and 0.0432 mV/mA, respectively.
CCM/GM Relative Skip Energy Control in Single-inductor Multiple-output DC-DC Converter for Wearable Device Power Solution
(2014)
Su, Yi-Ping
;
Lin, Chiun-He
;
Yang, Te-Fu
;
Huang, Ru-Yu
;
Chen, Wei-Chung
Compact size wearable devices require multiple supplies with relative large loading difference, which causes serious cross regulation, large ripple and oscillation in single-inductor multiple-output (SIMO) DC-DC converter. Thus, a continuous conduction mode/green mode (CCM/GM) relative skip energy control (RSEC) in single-inductor multiple-output (SIMO) is proposed for wearable device power solution. Different from conventional absolute skip method, the RSEC eliminates unnecessary skip-induced voltage ripple and cross regulation with well regulation performance over wide load and voltage ranges. Optimization between efficiency and voltage ripple achieves low noise supply and reduced switching loss. Moreover, smooth transition between CCM and GM provides high power and longer usage time in wearable devices. The test chip fabricated in 0.18 mu m CMOS process occupies 2.24mm(2) active area. Maximum output ripple, overshoot/undershoot and cross regulation are kept below 17mV, 27mV and 0.0432mV/mA, respectively.
Current-Mode Synthetic Control (CSC) Technique for High Efficiency DC-DC Boost Converters Over a Wide Load Range
(2011)
Su, Yi-Ping
;
Chen, Yi-Chun
;
Huang, Han-Hsiang
;
Lee, Yu-Huei
;
Yang, Yao-Yi
The proposed current-mode synthetic control (CSC) technique in the design of boost converters can improve the transient response time and maintain high conversion efficiency over a wide load range. The CSC technique has high accuracy similar to the current-mode control and doesn't need the slope compensation for simplicity. Besides, the transient response is also improved due to the current-mode hysteresis control. The load-dependent switching frequency at light loads results in high power conversion efficiency. Experimental results show that the output voltage ripple can be kept smaller than 50mV over a wide load current range from 0mA to 400mA with power conversion efficiency higher than 90% at load current of 10mA.
Current-Mode Synthetic Control Technique for High-Efficiency DC-DC Boost Converters Over a Wide Load Range
(2014-08-01)
Su, Yi-Ping
;
Luo, Yean-Kuo
;
Chen, Yi-Chun
;
Chen, Ke-Horng
;
交大名義發表
This paper proposes a current-mode synthetic control (CSC) technique for the design of boost converters to overcome the difficulty in designing a current-ripple hysteresis boost converter and to maintain high conversion efficiency over a wide load range. The CSC technique has a high accuracy because of the additional voltage path through the error amplifier. A smooth load transient response is maintained when the operation transits from continuous conduction mode with a nearly constant switching frequency to discontinuous conduction mode with a load-dependent switching frequency. Generally, ripple performance, light-load efficiency, and switching frequency are traded off in the design of hysteresis control regulator. In this paper, a balance among the load-dependent switching frequencies at light loads results in high power conversion efficiency compared with conventional pulsewidth modulation converter and attains compact ripple performance. The experimental results show that the output voltage ripple can be kept <50 mV over a wide load current range from 10 to 400 mA, where as power conversion efficiency is maintained at 78% at a load current of 10 mA when the switching frequency is decreased from 5 to 2 MHz.
Delay-Lock-Loop-Based Inductorless and Electrolytic Capacitorless Pseudo-Sine-Current Controller in LED Lighting Systems
(2015-12-01)
Chiu, Shao-Wei
;
Kuo, Chun-Chieh
;
Su, Yi-Ping
;
Chen, Ke-Horng
;
電控工程研究所
Light-emitting diode lighting system with the proposed pseudo-sine-current controller removes most of the external passive components, which include inductor, electrolytic capacitor, freewheel diode, blocking diode, and the bleeding circuit for Triac dimming control, for low cost and small volume. Delay-lock loop control can ensure the in-phase operation of ac input voltage and current for high power factor (PF) and low total harmonic distortion (THD). In addition, redundant power loss in Triac dimming control is eliminated to get a high efficiency of 85%. Furthermore, a high PF of 0.997 and a low THD of 7.74% are also achieved owing to in-phase line voltage and current.
Dynamic Sawtooth Compensation (DSC) Technique with Self-tuning Mode Selection (SMS) for Current-Mode Buck-Boost Converter
(2012)
Su, Yi-Ping
;
Wang, Shih-Wei
;
Lee, Yu-Huei
;
Chen, Ke-Horng
;
電控工程研究所
the current-mode Buck-Boost (BB) converter with the proposed dynamic sawtooth compensation (DSC) technique is able to improve transient response and system stability. To prevent the system switches between buck and boost operations once input and output are nearly equivalent, self-tuning mode selection (SMS) is proposed to decrease output ripple and redundant power consumption by eliminating the mode misjudgment. The duty cycle is decided by the output of error amplifier and sawtooth signal, which can be adequately adjusted to ensure small output ripple and thus to improve efficiency. Besides, the DSC and SMS technique can reduce the inductor current level and the numbers of switching to decrease switching and conduction losses for high efficiency. The converter with the switching frequency of IMHz was fabricated in IP3M 0.25-mu m CMOS process. The input voltage is in the range of 2.7V to 4.8V for battery-powered devices. The efficiency is higher than 88% when load ranges from 100mA to 400mA.
Implantable Biomedical Device Supplying by a 28nm CMOS Self-Calibration DC-DC Buck Converter with 97% Output Voltage Accuracy
(2015)
Yang, Te-Fu
;
Huang, Ru-Yu
;
Su, Yi-Ping
;
Balakumar
;
Chen, Ke-Horng
Implantable devices like artificial cardiac pacemakers are generally used to control irregular pulses of heart. For 10-year usage, high accuracy supply voltage is essential with the unavoidable aging of the power system to achieve near-natural beat rhythm. A Self-Calibration DC-DC Buck converter (SC-Buck) is proposed to achieve high output voltage accuracy by eliminating offset caused by mismatch of process, voltage and temperature (PVT). Furthermore, the discontinuity which affects transient performance in conventional offset cancellation is also overcome. Large area occupation, which is required to decrease mismatch in conventional operational amplifier, can be largely decreased according to Monte Carlo analysis. Without trimming process, the proposed SC-Buck technique achieves high accuracy for long-term usage (years) and low cost. The test chip fabricated in UMC 28nm CMOS process proves the output voltage accuracy of 97% since the mismatch of error amplifier can be suppressed from 122% to 1%.