Browsing by Author "Sun, JYC"

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A floating well method for exact capacitance-voltage measurement of nano technology
(2003-06-01)
Su, HD
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Chiou, BS
;
Wu, SY
;
Chang, MH
;
Lee, KH
Small gate area with short gate length reduces the C-V distortion of ultrathin oxide devices, but results in high parasitic capacitance/total capacitance ratio. The floating well method can exclude the parasitic capacitance to obtain accurate inversion oxide thickness without using any dummy pattern. It is suitable for nano technology.
Arsenic/phosphorus LDD optimization by taking advantage of phosphorus transient enhanced diffusion for high voltage input/output CMOS devices
(2002-01-01)
Wang, HCH
;
Wang, CC
;
Diaz, CH
;
Liew, BK
;
Sun, JYC
Optimization of a LDD doping profile to enhance hot carrier resistance in 3.3 V input/output CMOS devices has been performed by utilizing phosphorus transient enhanced diffusion (TED). Hot carrier effects in hybrid arsenic/phosphorus LDD nMOSFET's with and without TED are characterized comprehensively. Our result shows that the substrate current in a nMOSFET with phosphorus TED can be substantially reduced as compared to the one without TED. The reason is that the TED effect can yield a more graded n(-) LDD doping profile and thus a smaller lateral electric field. Further improvement of hot carrier reliability can be achieved by optimizing arsenic implant energy. Secondary ion mass spectrometry analysis for TED effect and two-dimensional (2-D) device simulation for electric field
Bi-mode breakdown test methodology of ultrathin oxide
(2003-12-01)
Su, HD
;
Chiou, BS
;
Ko, CY
;
Wu, SY
;
Chang, MH
The breakdown detections of ultrathin oxide (1.4-2 nm) using a fast voltage ramp have been studied. It was found that the breakdown voltage test of deep sub-micron technology requires the reduction of the gate area of test patterns and therefore the increase of the number of structures due to a large inversion gate current at a low electrical field (> 0. 1 A/cm(2) at 1 V) caused by the scaling down of oxide thickness. The gate current in accumulation mode is smaller than that in inversion mode by more than two orders of magnitude at a low applied voltage (1 V). The bi-mode model proposed in this paper applies a voltage stress in the inversion mode and detects failure in the accumulation mode to enhance the robustness of the breakdown test and reduce the possibility of pseudo breakdown failure. With the proposed method, a shorter test time with an increased test pattern area to improve the efficiency of the breakdown test of ultrathin oxide is achieved.
Characteristics of oxide breakdown and related impact on device of ultrathin (2.2 nm) silicon dioxide
(2003-09-01)
Su, HD
;
Chiou, BS
;
Wu, SY
;
Chang, MH
;
Lee, KH
The oxide breakdown characteristics of ultrathin oxide (2.2 nm) have been studied in this paper. Light emission microscopy (EMMI) analysis shows that each breakdown has a specific failure location with a random distribution. Gate leakage current increases for all soft breakdown events are similar. After soft breakdown, the I-V curve still shows the representative direct tunneling characteristics and can be fitted using a dual direct tunneling (DDT) model. Soft breakdown has no effect on the drain current of long-channel devices. Breakdown at the polyedge appears to be of the hard-breakdown mode and results in an abrupt increase in gate current. For short-channel devices, the polyedge is always within the damaged region of an oxide because the channel is shorter than the damaged region of the oxide. Hence, only hard breakdown resulting in permanent damage is observed in short-channel devices.
Hot carrier reliability improvement by utilizing phosphorus transient enhanced diffusion for input/output devices of deep submicron CMOS technology
(2000-12-01)
Wang, HCH
;
Diaz, CH
;
Liew, BK
;
Sun, JYC
;
Wang, TH
This letter presents a deep submicron CMOS process that takes advantage of phosphorus transient enhanced diffusion (TED) to improve the hot carrier reliability of 3.3 V input/output transistors, Arsenic/phosphorus LDI) nMOSFETs with and without TED are fabricated. The TED effects on a LDD junction profile, device substrate current and transconductance degradation are evaluated, Substantial substrate current reduction and hot carrier lifetime improvement for the input/output devices are attained due to a more graded n(-) LDD doping profile by taking advantage of phosphorus TED.
Improving the RF performance of 0.18 mu m CMOS with deep n-well implantation
(2001-10-01)
Su, JG
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Hsu, HM
;
Wong, SC
;
Chang, CY
;
Huang, TY
The radio-frequency (RF) figures of merit of 0.18 mum complementary metal-oxide-semiconductor (CMOS) technology are investigated by evaluating the unity-current-gain cutoff frequency (F-t) and maximum oscillation frequency (F-max). The device fabricated with an added deep n-well structure is shown to greatly enhance both the cutoff frequency and the maximum oscillation frequency, with negligible dc disturbance. Specifically, 18% increase in F-t and 25% increase in F-max are achieved. Since the deep n-well implant can be easily adopted in a standard CMOS process, the approach appears to be very promising for future CMOS RF applications.