Browsing by Author "Sung, Wen-Li"

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Asymmetric Characteristic Fluctuation of Undoped Gate-All-Around Nanowire MOSFETs Induced by Random Discrete Dopants inside Source/Drain Extensions
(2017-01-01)
Sung, Wen-Li
;
Li, Yiming
;
資訊工程學系
;
電機工程學系
;
電信工程研究所
We perform experimentally validated statistical device simulation to explore characteristic fluctuation induced by random discrete dopants (RDDs) inside the source / drain extensions of undoped gate-all-around silicon nanowire MOSFETs. The engineering findings of this study indicate that both the DC and dynamic characteristic fluctuation caused by RDDs of the drain extension has relatively smaller variability than that caused by RDDs of the source extension. It could be attributed to the effect of random position of RDDs appearing in the source / drain extensions. Compared to RDDs of the source extension, fluctuations of voltage gain and cut-off frequency of the explored gate-all-around silicon nanowire MOSFET circuit induced by RDDs of the drain extension can be significantly reduced from 24.3% and 20.7% to 0.9% and 2.2%, respectively.
DC/AC/RF Characteristic Fluctuations Induced by Various Random Discrete Dopants of Gate-All-Around Silicon Nanowire n-MOSFETs
(2018-06-01)
Sung, Wen-Li
;
Li, Yiming
;
電信工程研究所
;
Institute of Communications Engineering
In this paper, we explored the characteristic fluctuations induced by various random discrete dopants (RDDs) on gate-all-around silicon nanowire metal-oxide semiconductor field-effect transistors. A 3-D quantum-mechanically corrected transport model was employed to analyze the simulated devices. The statistical results indicate that the variation of threshold voltage (Vth) not only can be reduced from 28.6% to 10.7% without channel doping and penetration from the source/drain into the channel, but also the variation of 3-dB frequency can be reduced from 8% to 2.7% due to the reduction of the variation of Vth. We reported that the high-frequency characteristic fluctuations (voltage gain and cutoff frequency) were dominated by electron mobility. This caused by RDDs from the drain extension exhibited less variability than that caused by RDDs from the source extension due to a reduced injection velocity near the S side and a negligible difference in the electron saturation velocity near the D side. This paper provides pertinent information on the design of high-frequency amplifier circuits in relation to devices with RDDs induced by variations in the semiconductor process.
Effects of random number and location of the nanosized metal grains on the threshold voltage variability of silicon gate-all-around nanowiren-type metal-oxide-semiconductor field-effect transistors
(1970-01-01)
Sung, Wen-Li
;
Li, Yiming
;
交大名義發表
;
電機工程學系
;
電信工程研究所
In this study, the effect of the metal grain number (MGN) and metal grain location (MGL) with a low/high work function (WK) on the variability of the threshold voltage (sigma V-th) of silicon gate-all-around nanowiren-type metal-oxide-semiconductor field-effect transistors was examined by using an experimentally validated cuboid grain method. For the effect of the MGN,sigma V(th)induced by WK fluctuations strongly depended on the MGN for the same metal-gate area. For the effect of the MGL, metal grains with a low WK near the source (S) side are crucial for the magnitude of sigma V-th. Therefore, for the weighted superposition of the WK with each metal grain, the number of metal grains with a low WK near theSside may alter the distribution ofV(th)and dominate the magnitude of sigma V-th.
Statistical Device Simulation of Characteristic Fluctuation of 10-nm Gate-All-Around Silicon Nanowire MOSFETs Induced by Various Discrete Random Dopants
(2016)
Sung, Wen-Li
;
Chang, Han-Tung
;
Chen, Chieh-Yang
;
Chao, Pei-Jung
;
Li, Yiming
We study the impact of random dopant fluctuation (RDF) on electrical characteristics of 10-nm-gatehigh kappa/metal gate gate-all-around silicon nanowire MOSFET devices. To provide the best accuracy of device simulation, model parameters are validated by using full quantum mechanical simulation and calibrated with experimental results. Physical mechanism of RDs inside channel and penetration from the source/drain extensions into the channel is discussed. Electrical characteristic of the device is estimated with respect to different types of RDF.
Statistical Prediction of Nanosized-Metal-Grain-Induced Threshold-Voltage Variability for 3D Vertically Stacked Silicon Gate-All-Around Nanowiren-MOSFETs
(1970-01-01)
Sung, Wen-Li
;
Li, Yiming
;
交大名義發表
;
電機工程學系
;
電信工程研究所
In this study, we present a statistically accurate model to predict the threshold-voltage variability (sigma V-th) efficiently for three-dimensional (3D) vertically stacked silicon (Si) gate-all-around (GAA) nanowire (NW)n-MOSFETs with multi-channels. The statistical results indicate that the sigma V(th)decreases exponentially by increasing metal grain number (MGN), which is unitless. Additionally, the magnitude of sigma V(th)was calculated for various MGNs, which joins the normality test with Anderson-Darling test. Therefore, the model with MGN can be implemented by nonlinear regression with a regression coefficient of approximately one. From this model and the perspective of process, more 3D vertically stacked channels can reduce the value and sensitivity of sigma V-th. This study provides useful information from statistics to explain the experiment results for 3D vertically stacked Si GAA NWn-MOSFETs with multi-channels.
Timing and Power Fluctuations on Gate-All-Around Nanowire CMOS Circuit Induced by Various Sources of Random Discrete Dopants
(2017-01-01)
Sung, Wen-Li
;
Chao, Pei-Jung
;
Li, Yiming
;
分子醫學與生物工程研究所
;
電信工程研究所
Random dopant fluctuation (RDF) is one of fluctuation sources in sub-7-nm semiconductor technology node. In this paper, we estimate the timing and power fluctuations on 10-nm-gate gate-all-around (GAA) silicon nanowire (NW) complementary metal-oxide-semiconductor (CMOS) circuit induced by various random discrete dopants (RDDs) from channel (with/without doping), source/drain (S/D) extensions and penetration from S/D extensions. The 3D quantum mechanical transport and non-equilibrium Green's function (NEGF) models were used for the NW CMOS circuit. The experimentally validated device simulation indicates that at a similar threshold voltage, CMOS devices without channel doping possess 49.5% reduction on the normalized fluctuation of the static power consumption due to the reduction of sigma V-th and sigma I-off. The normalized fluctuation of dynamic power is comparable with/without channel doping due to small variation of the gate capacitance. Because of reduction of sigma I-sat, the normalized fluctuation of short-circuit power of CMOS circuit was reduced from 21.7% to 10.2% without channel doping. And, we found that the uctuations of the timing, noise margin (NM) and power consumption of the NW CMOS circuit follow the trend of sigma V-th. From the point of view of N-/P-type NW MOSFETs caused by RDF, this study may show the fluctuation of CMOS circuit performance highly influenced by the key parameters of N-/P-type NW MOSFETs.