Statistical Prediction of Nanosized-Metal-Grain-Induced Threshold-Voltage Variability for 3D Vertically Stacked Silicon Gate-All-Around Nanowiren-MOSFETs

Abstract

In this study, we present a statistically accurate model to predict the threshold-voltage variability (sigma V-th) efficiently for three-dimensional (3D) vertically stacked silicon (Si) gate-all-around (GAA) nanowire (NW)n-MOSFETs with multi-channels. The statistical results indicate that the sigma V(th)decreases exponentially by increasing metal grain number (MGN), which is unitless. Additionally, the magnitude of sigma V(th)was calculated for various MGNs, which joins the normality test with Anderson-Darling test. Therefore, the model with MGN can be implemented by nonlinear regression with a regression coefficient of approximately one. From this model and the perspective of process, more 3D vertically stacked channels can reduce the value and sensitivity of sigma V-th. This study provides useful information from statistics to explain the experiment results for 3D vertically stacked Si GAA NWn-MOSFETs with multi-channels.