Browsing by Author "TSUI, BY"

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A NOVEL PROCESS FOR HIGH-PERFORMANCE SCHOTTKY-BARRIER PMOS
(1988-03-01)
TSUI, BY
;
CHEN, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A NOVEL PROCESS FOR HIGH-PERFORMANCE SCHOTTKY-BARRIER PMOS
(1989-05-01)
TSUI, BY
;
CHEN, MC
;
電控工程研究所
;
Institute of Electrical and Control Engineering
CONTACT RESISTIVITY OF SHALLOW JUNCTIONS FORMED BY IMPLANTATION THROUGH PT OR PTSI
(1992-09-01)
TSUI, BY
;
CHEN, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The specific contact resistance (rho(c)) of PtSi/p+ and PtSi/n+ contacts formed by ion implantation through Pt or PtSi was studied. A simple process to form self-aligned six-terminal Kelvin structure was developed in order to measure the specific contact resistance. For the PtSi/p+ contact system, a rho(c) lower than 1 x 10(-6) OMEGA-cm2 was achieved by BF2+ implantation at 40 keV to a dose of 5 x 10(15) cm-2. Increase of dose or energy could further decrease the rho(c) to be lower than 5 x 10(-7) OMEGA-cm2. The rho(c) of the PtSi/n+ contact system was lower than that of the PtSi/p+ contact system and a rho(c) of 1 x 10(-7) OMEGA-cm2 was obtained. These results indicate that although the PtSi-contacted junction is formed at temperatures lower than 800-degrees-C, the rho(c) is low enough to satisfy the requirements of submicrometer technology. We suggest that PtSi should be a favorable material to form shallow junctions and contacts simultaneously for future VLSI processes and to satisfy low thermal budget requirement.
DIELECTRIC DEGRADATION OF PT/SIO2/SI STRUCTURES DURING THERMAL ANNEALING
(1993-04-01)
TSUI, BY
;
CHEN, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Traditionally it was believed that platinum does not interact with silicon dioxide during thermal treatment in an N2 ambient. In this work, however, dielectric degradation of the Pt/SiO2/Si structure during thermal annealing was observed. The density of surface states at the SiO2/Si interface increases and the dielectric strength of the oxide decreases after annealing at temperatures higher than 600-degrees-C. Ion implantation through the Pt/SiO2 structure enhances the degradation. After removal of the Pt film, a second annealing can reduce the surface state density but the dielectric strength cannot be recovered. Although material analysis such as AES and SIMS shows no obvious differences between the fresh SiO2 and the degraded SiO2, electrical analyses indicate that thermal stress is responsible for the increase of the surface states while Pt dissolving in SiO2 is responsible for the decrease of the dielectric strength. Thus, the process sequence should be taken into consideration for practical application.
EFFECT OF FLUORINE INCORPORATION ON THE THERMAL-STABILITY OF PTSI/SI STRUCTURE
(1993-01-01)
TSUI, BY
;
TSAI, JY
;
WU, TS
;
CHEN, MC
;
交大名義發表
The effect of fluorine incorporation on PtSi/Si structure is studied systematically. It is observed that the fluorine incorporation from ion implantation improves the high-temperature stability of the PtSi/Si structure. The optimum implantation energy is determined to be the energy at which the maximum percentage of the as-implanted fluorine ion locates at the PtSi/Si interface region. The SIMS analysis shows that the fluorine atom piles up at the PtSi/Si interface. The XPS analysis indicates that the fluorine atoms at the PtSi/Si interface are bonded to the silicon atoms in a form of SiF2 or SiF3. A fluorine-buffer (FB) model is proposed to explain the effect of fluorine incorporation. It is postulated that the Si-F layer acts as a buffer layer to change the PtSi/Si interface energy and preserve the integrity of the silicide layer at high temperature. Fluorinated Schottky junctions are fabricated and the electrical characteristics show that the sustainable process temperature can be improved from 650-degrees-C for the unfluorinated Schottky junctions to higher than 800-degrees-C for the fluorinated Schottky junctions.
FORMATION AND CHARACTERIZATION OF A PTSI CONTACTED N+P SHALLOW JUNCTION
(1990-09-01)
TSUI, BY
;
CHEN, MC
;
交大名義發表
;
電控工程研究所
;
National Chiao Tung University
FORMATION OF 0.1-MU-M N+ P JUNCTION BY AS+ IMPLANTATION THROUGH PT OR PTSI FILM
(1990-04-01)
TSUI, BY
;
CHEN, MC
;
交大名義發表
;
電控工程研究所
;
National Chiao Tung University
FORMATION OF PTSI-CONTACTED P+N SHALLOW JUNCTIONS BY BF2+ IMPLANTATION AND LOW-TEMPERATURE FURNACE ANNEALING
(1991-04-15)
TSUI, BY
;
TSAI, JY
;
CHEN, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work investigates the characteristics of PtSi-silicided p+n shallow junctions fabricated by implanting BF2+ ions into either the Pt/Si (ITM scheme) or the PtSi/Si (ITS scheme) structure followed by annealing in N2 furnace at temperatures from 650 to 800-degrees-C. For a structure with Pt film of 30 nm thickness or PtSi film of 60 nm thickness, the implantation energy ranges from 40 to 80 keV with a dose ranging from 1 x 10(15) to 1 x 10(16) cm-2. For the ITS samples with BF2+ implantation at 40 keV, all ions are confined in the PtSi layer; therefore, only a modified Schottky junction is formed by the diffusion of boron atoms from the PtSi film during the annealing. The junction depth may be as shallow as 30 nm from the PtSi/Si interface. A complete p+n junction is formed for the ITM samples with implantation at 40 keV as well as all the samples implanted at 80 keV. The junction thus obtained has a forward ideality factor lower than 1.02 and a reverse current density less than 0.2 nA/cm2 at -5 V. Activation energy measurement indicates that most of the implantation damages have been recovered after annealing at a temperature as low as 700-degrees-C. The reverse area and peripheral leakage current density are separated by measuring diodes of different perimeter/area ratio. For good samples, the reverse peripheral current comes from the surface generation current within the depletion region underneath the field oxide. All of the experimental results reveal that either Pt or PtSi film can be employed as an efficient barrier film in the ITM/ITS technique to form excellent and ultrashallow junctions with a low thermal budget.
HIGH-TEMPERATURE STABILITY OF PLATINUM SILICIDE ASSOCIATED WITH FLUORINE IMPLANTATION
(1990-04-01)
TSAI, JY
;
TSUI, BY
;
CHEN, MC
;
交大名義發表
;
電控工程研究所
LOW-TEMPERATURE REACTION OF THIN-FILM PLATINUM (LESS-THAN-OR-EQUAL-TO-300A) WITH (100) SILICON
(1990-12-15)
TSUI, BY
;
CHEN, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Thin platinum films of 164 and 303 angstrom thickness are deposited on (100) silicon and annealed at temperatures ranging from 180 to 300-degrees-C in a nitrogen furnace for various times ranging from 1 min to 200 h. Sheet resistance (R(s) measurement shows a four-stage silicide formation sequence: (1) the R(s) increases to a maximum value; (2) the R(s) then decreases to a minimum value; (3) the R(s) increases once again and reaches a second maximum value; and (4) the R(s) decreases to a final stable value. X-ray diffraction analysis indicates that the initial phase grown is Pt12Si5 which corresponds to the sheet-resistance increase in the first stage. This phase is also identified by the transmission electron diffraction analysis. This is the first time that the Pt12Si5 phase formed by the Pt/Si direct reaction is observed. The second stage corresponds to the growth of Pt2Si as confirmed by the x-ray diffraction and Auger spectroscopy analyses. The third stage corresponds to the growth of PtSi and the final stage corresponds to the increase of PtSi grain size. Samples with initial Pt films of 500, 800, and 2000 angstrom thickness were also prepared and analyzed by x-ray diffraction. The increase of film thickness suppresses the growth of Pt12Si5, and for Pt films thicker than 800 angstrom the initial phase grown becomes Pt2Si. The film thickness dependence is explained by the partial lattice-match-induced preferred phase growth effect. The effective absorption coefficient (K(se) of the Pt/Si structure after annealing is determined by ellipsometry measurement, and the activation energy of the Pt12Si5 phase formation derived from the R(s)-time plot or the K(se)-time plot is determined to be 1.5-1.6 eV.
ROLE OF FLUORINE-ATOMS ON THE THERMAL-STABILITY OF THE SILICIDE SILICON STRUCTURE
(1994-08-01)
TSUI, BY
;
CHEN, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
It has been known that thermal stability of the silicide/silicon system can be improved by fluorine incorporation. Two mechanisms have been proposed-the fluorine buffer model and the grain growth retardation model. This communication examines the validity of these two mechanisms. Fluorine ions are introduced into the PtSi/Si structure by implantation at various energies and to various dosages. If the fluorine ions are confined in the silicide layer, the grain growth is retarded, however, no improvement of the thermal stability can be obtained. On the other hand, if most of the implanted fluorine ions are located near the PtSi/Si interface, the grains of the fluorinated silicide film can grow to be larger than those of the unfluorinated silicide film without becoming discontinuous to the film. It is thus concluded that the fluorine accumulation at the interface, i.e., the fluorine buffer model, plays the dominant role on the thermal stability of the fluorinated PtSi/Si structure.
SERIES RESISTANCE OF SELF-ALIGNED SILICIDED SOURCE DRAIN STRUCTURE
(1993-01-01)
TSUI, BY
;
CHEN, MC
;
電子工程學系及電子研究所
;
電控工程研究所
;
Department of Electronics Engineering and Institute of Electronics
The external resistance of the self-aligned silicided source/drain structure is examined by two-dimensional simulation considering recession of the contact interface due to the consumption of silicon during the silicidation process. It is observed that the recessed contact interface forces a significant amount of current to flow into the high-resistivity part of the junction resulting in an increase of resistance as large as several hundred ohms-micrometers in comparison with the surface contact structure. The increase scales up with the scale-down of the minimum feature size, and the expected benefits of the SALICIDE structure become diminished for the sub-half-micrometer devices. A simple analytical explanation is proposed. The error between the analytical calculation and the two-dimensional simulation is within 20%. By considering the recession of the contact interface, the reported high external resistance of the short-channel MOSFET's is explained successfully. Different source/drain contact types are compared, and it is concluded that the conventional SALICIDE process should be modified for the sub-half-micrometer devices.