Browsing by Author "Tai, Ya-Hsiang"

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A low temperature polycrystalline silicon thin film transistor phase locked loop circuit used for clock regeneration
(2007)
Tai, Ya-Hsiang
;
Tseng, Chen-Yeh
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顯示科技研究所
;
Institute of Display
In this paper, a low temperature polycrystalline silicon (LTPS) thin film transistor (TFT) circuit of a phase locked loop (PLL) is proposed. Its performance is discussed and its high tolerance of device variation is demonstrated.
A new evaluation method of the threshold voltage for a low temperature poly-silicon thin film transistor in a source follower configuration
(2005)
Huang, Shi-Zhe
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Tai, Ya-Hsiang
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光電工程學系
;
Department of Photonics
A new evaluation method of the output voltage for the source follower composed of a LTPS TFT is proposed. This method provides an effective and more precise description about the unsaturated output voltage behaviour of the source follower with a LTPS TFT. A new interpretation of the threshold voltage of LTPS TFT is also provided.
A new pixel circuit for driving organic light emitting diodes with low temperature polycrystalline thin film transistors
(2005)
Chen, Bo-Ting
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Kuo, Yu-Ju
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Pai, Cheng-Chiu
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Tsai, Chun-Chien
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Cheng, Huang-Chung
A new active matrix organic light emitting diode (AM-OLED) pixel circuit design, based on the low-temperature polycrystalline thin-film transistors (LTPS-TFTs) is proposed and verified by SPICE simulation. The voltage-programming pixel circuit is formed by five n-type TFTs. one additional control signal, and a storage capacitor. The simulation results show that this pixel circuit has high immunity to the variation of poly-Si TFT characteristics.
A New Pixel Circuit for Driving Organic Light-Emitting Diode With Low Temperature Polycrystalline Silicon Thin-Film Transistors
(2005-09-01)
Tai, Ya-Hsiang
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Chen, Bo-Ting
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Kuo, Yu-Ju
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Tsai, Chun-Chien
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Chiang, Ko-Yu
A new pixel circuit design for active matrix organic light-emitting diode (AMOLED), based on the low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) is proposed and verified by SPICE simulation. Threshold voltage compensation pixel circuit consisting of four n-type TFTs, one p-type TFT, one additional control signal, and one storage capacitor is used to enhance display image quality. The simulation results show that this pixel circuit has high immunity to the variation of poly-Si TFT characteristics.
A new voltage driving pixel circuit for active matrix organic light emitting diodes
(2005)
Pai, Cheng-Chiu
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Tai, Ya-Hsiang
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光電工程學系
;
Department of Photonics
A new voltage driving pixel circuit composed of five TFTs and two capacitors for AMOLED is proposed. The simulation results indicate that the proposed circuit is effective to provide a uniform output characteristic against the variation in the poly-SI TFT performances.
A novel analogue buffer using poly-Si TFTs for active matrix displays
(2005)
Pai, Cheng-Chiu
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Tai, Ya-Hsiang
;
光電工程學系
;
Department of Photonics
A novel source-follower-type analogue buffer employing LTPS TFTs is proposed for AMLCD and AMOLED. The simulation results indicate that the proposed circuit is capable of minimizing the variation from both the charging time and the device characteristics and maximizing the range of the input voltage by adding an active load and a new compensation operation.
A statistical model for simulating the effect of UPS TFT device variation for SOP applications
(2007-12-01)
Tai, Ya-Hsiang
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Huang, Shih-Che
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Chen, Wan-Ping
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Chao, Yu-Te
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Chou, Yen-Pang
In this paper, the variation characteristics of low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) are investigated with a statistical approach. A special layout is proposed to investigate the device variation with respect to various devices distances. Two non-Gaussian equations are proposed to fit the device parameter distributions, whose the coefficients of determination (R(2)) are both near 0.9, reflecting the validity of the model. Two benchmark circuits are used to compare the difference between the proposed model and the conventional Gaussian distribution for the device parameter distribution. The output behaviors of the digital and analog circuits show that the variation in the short range would greatly affect the performance of the analog circuits and would instead be averaged in the digital circuits.
Abnormal Dual Channel Formation Induced by Hydrogen Diffusion From SiNx Interlayer Dielectric in Top Gate a-InGaZnO Transistors
(2017-03-01)
Chen, Guan-Fu
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Chang, Ting-Chang
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Chen, Hua-Mao
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Chen, Bo-Wei
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Chen, Hong-Chih
This letter investigates effects of different channel dimensions in top-gate a-InGaZnO4 thin-film transistors with SiNx interlayer dielectric. In narrow channel devices, hydrogen atoms in the SiNx layer diffuse into the entire active layer, inducing a single channel. However, in wider channel devices, the diffusion distance for hydrogen atoms is insufficient to affect the whole channel, instead inducing a double channel. In addition, under hot carrier stress, narrow and wide channels exhibit different degradation behaviors, with simulations showing a strong electrical field at IGZO near the drain terminal of the main channel, which is unaffected by hydrogen.
Abnormal hump in capacitance-voltage measurements induced by ultraviolet light in a-IGZO thin-film transistors
(2017-01-09)
Tsao, Yu-Ching
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Chang, Ting-Chang
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Chen, Hua-Mao
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Chen, Bo-Wei
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Chiang, Hsiao-Cheng
This work demonstrates the generation of abnormal capacitance for amorphous indium-gallium-zinc oxide (a-InGaZnO4) thin-film transistors after being subjected to negative bias stress under ultraviolet light illumination stress (NBIS). At various operation frequencies, there are two-step tendencies in their capacitance-voltage curves. When gate bias is smaller than threshold voltage, the measured capacitance is dominated by interface defects. Conversely, the measured capacitance is dominated by oxygen vacancies when gate bias is larger than threshold voltage. The impact of these interface defects and oxygen vacancies on capacitance-voltage curves is verified by TCAD simulation software. Published by AIP Publishing.
Abnormal sub-threshold swing degradation under dynamic hot carrier stress in HfO2/TiN n-channel metal-oxide-semiconductor field-effect-transistors
(2013-07-08)
Tsai, Jyun-Yu
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Chang, Ting-Chang
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Lo, Wen-Hung
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Chen, Ching-En
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Ho, Szu-Han
This work finds abnormal sub-threshold swing (S.S.) degradation under dynamic hot carrier stress (HCS) in n-channel metal-oxide-semiconductor field-effect-transistors with high-k gate dielectric. Results indicate that there is no change in S.S. after dynamic HCS due to band-to-band hot hole injection at the drain side which acts to diminish the stress field. Moreover, the impaired stress field causes the interface states to mainly distribute in shallow states. This results in ON state current and transconductance decreases, whereas S.S. degradation is insignificant after dynamic HCS. The proposed model is confirmed by one-side charge pumping measurement and gate-to-drain capacitance at varying frequencies. (C) 2013 AIP Publishing LLC.
Abnormal Subthreshold Leakage Current at High Temperature in InGaZnO Thin-Film Transistors
(2012-04-01)
Chang, Geng-Wei
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Chang, Ting-Chang
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Jhu, Jhe-Ciou
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Tsai, Tsung-Ming
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Syu, Yong-En
Abnormal subthreshold leakage current is observed at high temperature in amorphous InGaZnO thin-film transistors. The transfer curve exhibits an apparent subthreshold current stretch-out phenomenon that becomes more serious with increasing temperatures. The negative bias temperature instability experiment has been used to prove high-temperature-induced hole generation. Furthermore, the transfer characteristics with different drain voltages have been also used to confirm the status of hole accumulation. These pieces of evidence clearly defined the stretch-out phenomenon, which is caused by thermal-induced hole generation and accumulation at the source region that leads to source-side barrier lowering.
Abnormal threshold voltage shift under hot carrier stress in Ti1-xNx/HfO2 p-channel metal-oxide-semiconductor field-effect transistors
(2013-09-28)
Tsai, Jyun-Yu
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Chang, Ting-Chang
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Lo, Wen-Hung
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Ho, Szu-Han
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Chen, Ching-En
This work investigates the channel hot carrier (CHC) effect in HfO2/Ti1-xNx p-channel metal oxide semiconductor field effect transistors (p-MOSFETs). Generally, the subthreshold swing (S. S.) should increase during CHC stress (CHCS), since interface states will be generated near the drain side under high electric field due to drain voltage (V-d). However, our experimental data indicate that S. S. has no evident change under CHCS, but threshold voltage (V-th) shifts positively. This result can be attributed to hot carrier injected into high-k dielectric near the drain side. Meanwhile, it is surprising that such V-th degradation is not observed in the saturation region during stress. Therefore, drain-induced-barrier-lowering (DIBL) as a result of CHC-induced electron trapping is proposed to explain the different V-th behaviors in the linear and saturation regions. Additionally, the influence of different nitrogen concentrations in HfO2/Ti1-xNx p-MOSFETs on CHCS is also investigated in this work. Since nitrogen diffuses to SiO2/Si interface induced pre-N-it occurring to degrades channel mobility during the annealing process, a device with more nitrogen shows slightly less impact ionization, leading to insignificant charge trapping-induced DIBL behavior. (C) 2013 AIP Publishing LLC.
Active in-cell touch circuit using floating common electrode as sensing pad for the large size in-plane-switching liquid crystal displays
(2017-10-01)
Tai, Ya-Hsiang
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Lin, Chi-Hao
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Cheu, Wei-Jia
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光電工程學系
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Department of Photonics
In this paper, we propose an in-cell active touch circuit using the concept of floating common electrode for large size in-plane-switching liquid crystal displays. Compared with the conventional passive in-cell touch circuit, the proposed method can greatly reduce the readout channel numbers by sharing the sensing bus for one column. Because the touch signal is amplified in the pixel, the touch panel can be easily scaled up in size. Simulation results show that the difference between touch and no-touch signals can be as large as 10A even with threshold voltage shift of +/- 1V. The possible issues of the proposed method are experimentally verified.
Active matrix touch sensor detecting time-constant change implemented by dual-gate IGZO TFTs
(2012-06-01)
Tai, Ya-Hsiang
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Chiu, Hao-Lin
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Chou, Lu-Sheng
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光電工程學系
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顯示科技研究所
The dual-gate IGZO TFT is proposed to be used in an active matrix touch sensing circuit. The circuit contains only one TFT with a RC low-pass filter, since the dual-gate IGZO TFT can be controlled by both its top and bottom gates. The simplest structure maximizes the sensing pad area in the pixel. A touch event on the sensing pad forms a capacitance and thus increases the RC time-constant of the scan pulse fed to the gate of TFT. Thus, a significant transient ON current is generated to be the sensing signal. The current is so large that it can be easily read out and thus the power and cost of peripheral ICs can be reduced. In this paper, the robustness of the circuit to environment in operations is discussed. (c) 2012 Elsevier Ltd. All rights reserved.
Active Photo-Sensing Array of Thin Film Transistor with Threshold Voltage Compensation
(2012)
Chou, Lu-Sheng
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Chen, Huo Moun
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Chen, Bo-Cheng
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Zhang, Jun-Yi
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Tai, Ya-Hsiang
In this paper, an active photo-sensing amplifier pixel circuit with compensation function of device variation is proposed, which has high aperture ratio since only 3 TFTs are used. The compensation function of the circuit obviously improves the sensing error resulted from device variation from 80% to 6%.
Advanced gate-all-around fin-like poly-Si TFTs with multiple nanowire channels
(2008)
Tu, Shih-Wei
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Liao, Ta-Chuan
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Lin, Wei-Kai
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Liu, Cheng-Chin
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Tai, Ya-Hsiang
The gate-all-around (GAA) fin-like poly-Si TFTs (FinTFTs) with multiple nanowire channels (MNCs) have been fabricated using a simple process to demonstrate high performance electrical characteristics. The fin-like nanowire (NW) channel with high body thickness-to-width ratio (T-Fin/W-Fin), approximately equals to one, was realized only with a sidewall-spacer formation. The unique suspending MNCs were also achieved to build the GAA structure. By the way, the GAA-MNC Fin TFTs showed outstanding three-dimensional gate controllability and excellent electrical characteristics, which revealed a high ON/OFF current ratio (>10(8)), a low threshold voltage, a steep subthreshold swing, a near-free drain-induced barrier lowering and a good reliability. Therefore, such the high-performance GAA-MNC FinTFTs are vet-v suitable for the applications in the system-on-panel (SOP) and three-dimensional (3D) circuits.
An Empirical Defect-Related Photo Leakage Current Model for LTPS TFTs Based on the Unit Lux Current
(2010-05-01)
Tai, Ya-Hsiang
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Kuo, Yan-Fu
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Sun, Guo-Pei
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光電工程學系
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顯示科技研究所
In this paper, the photosensitive effect of n-type low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) after dc stress is analyzed. It is found that the illumination behaviors for poly-Si TFTs are dependent on the defect types created by different stress conditions of hot-carrier and self-heating effects. For a given stress-induced device degradation, the anomalous illumination behaviors are observed, and these photo-induced leakage currents are not included in the present SPICE device model. Therefore, based on trap-assisted and Poole-Frenkel effect, an empirical defect-related photo leakage current model based on Unit Lux Current (ULC) is proposed to depict the photo-induced current after device degradation. Furthermore, the verified equation of ULC is analytically derived and has good agreement with the experimental data.
An external compensation method for AMOLED using the concept of ramp-stop
(2017-11-01)
Tai, Ya-Hsiang
;
Lin, Chi-Hao
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電機學院
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光電工程學系
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College of Electrical and Computer Engineering
In this paper, we propose an external feedback method to compensate the device variation for active-matrix organic light-emitting diode. The pixel data current is controlled by ramping the gate voltage and converted to the sensed voltage V-sense in real time. When V-sense is equal to a preset voltage V-data, the switching block outputs the low potential to stop the ramping. Therefore, the gate voltage is locked at the value corresponding to the target data current. This circuit is implemented with three thin-film transistors in the active area and some functional blocks in driver integrated circuit (IC), namely, sentinel block, current-voltage converting block, and switching block. Unlike the other usual methods of external compensation requiring double number of connections between driver IC and glass, by using the common ramping signal and a simple circuit made on glass, the proposed method can be implemented with only one pin per column.
Analysis of Anomalous Capacitance Induced by TAGIDL in p-Channel LTPS TFTs
(2010)
Lin, Chia-Sheng
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Chen, Ying-Chung
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Chang, Ting-Chang
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Li, Hung-Wei
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Chen, Shih-Ching
In this work, a mechanism of anomalous capacitance in p-channel low temperature polycrystalline silicon thin film transistors (LTPS TFTs) was investigated. In general, the effective capacitance of the LTPS TFTs was only dependent with the overlap area between the gate and source/drain under the off-state. However, the experimental results reveal that the off-state capacitance was increased with decreasing measurement frequency and/or with increasing measurement temperature. By fitting the curve of the drain current vs electric field under off-state region, it was verified that the trap-assisted gate-induced drain leakage (TAGIDL) consists of the Pool-Frenkel emission and thermal field emission. In addition, the charge density calculated from the C(gsd)-V(g) measurement also has the same dependence with electric field. This result demonstrates that the anomalous capacitance is mainly due to the TAGIDL. To suppress the anomalous capacitance, a band-to-band hot electron stress was utilized to reduce the vertical electric field between the gate and the drain. The electric field simulation was also performed by TCAD software. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3483759] All rights reserved.
Analysis of P-type poly-Si TFT degradation under dynamic gate voltage stress using the slicing model
(2007)
Huang, Shih-Che
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Tsao, Hung-Chuan
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Tai, Ya-Hsiang
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光電工程學系
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Department of Photonics
In this work, the mobility degradation after gate AC stress in the off region are examined. It is discovered that the mobility increases after AC gate stress condition 0 V to + 15 V, which the previously reported model (by Uraoka. Y) may not explain. Considering the spatial distribution of the voltage and the flow of the carriers in the channel, we proposed the slicing model", that is, replace the original TFT by ten TFTs with shorter channel length. Then, by applying the circuit simulator, the voltage distribution in the channel under different stages of gate applied voltage may be obtained. An index considering the current flow and the channel voltage at the edge nodes are proposed to describe the degradation in mobility. The fair linearity between the proposed index and the degradation in mobility reveals the validity of the proposed model.