Browsing by Author "Tang, Chun-Jung"

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A Novel Hot-Electron Programming Method in a Buried Diffusion Bit-Line SONOS Memory by Utilizing Nonequilibrium Charge Transport
(2009-02-01)
Wang, Tahui
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Tang, Chun-Jung
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Li, C. -W.
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Lee, Chih Hsiung
;
Ou, T. -F
We propose a new hot-electron programming method with a low drain-to-source voltage in a buried-diffusion (BD) bit-line SONOS memory array. In this method, channel electrons are preaccelerated in a cell preceding a program cell. For a small bit-line width, some energetic electrons will traverse an n(+) BD region and enter a program cell with residual energy due to nonequilibrium transport. Our measurement result shows that this residual energy can significantly enhance hot-electron programming efficiency even at a V(ds) of 2.5 V. The concept of this method is verified by means of a Monte Carlo analysis. Our study shows that this method is more effective as a bit-line width reduces.
Characteristics and physical mechanisms of positive bias and temperature stress-induced drain current degradation in HfSiON nMOSFETs
(2006-06-01)
Chan, Chien-Tai
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Tang, Chun-Jung
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Wang, Tahui
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Wang, Howard C. -H.
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Tang, Denny D.
Drain current degradation in HfSiON gate, dielectric nMOSFETs by positive gate bias and temperature stress is investigated by using a fast transient measurement technique. The degradation exhibits two stages, featuring a different degradation rate and stress temperature dependence. The first-stage degradation is attributed to the charging of preexisting high-k dielectric traps and has a log(t) dependence on stress time, whereas the second-stage degradation is mainly caused by new high-k trap creation. The high-k trap growth rate is characterized by two techniques, namely 1) a recovery transient technique and 2) a charge-pumping technique. Finally, the effect of processing on high-k trap growth is evaluated.
Characterization and Monte Carlo analysis of secondary electrons induced program disturb in a buried diffusion bit-line SONOS flash memory
(2007)
Tang, Chun-Jung
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Li, C. W.
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Wang, Tahui
;
Gu, S. H.
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Chen, P. C.
A new program disturb in a buried diffusion bit-line SONOS array is observed as a bit-line width is reduced. A multi-step Monte Carlo simulation is performed to explore the disturb mechanism. We find that the V, shift of a disturbed cell is attributed to impact ionization-generated secondary electrons in a neighboring cell when it is in programming. The effects of substrate bias, bit-line dimension and pocket implant on the program disturb are characterized and evaluated by a Monte Carlo simulation.
Investigation of the strained PMOS on (110) substrate
(2007)
Tang, Chun-Jung
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Huang, Shih-Hian
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Wang, Tahui
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Chang, Chih-Sheng
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電子工程學系及電子研究所
This paper performed a detail study on the strained PMOS fabricated on the (I 10) Si substrate. We showed that in the (I 10) plane, the four-fold symmetry direction, <111(,)>, has the ideal band-structure features for the uniaxial-process-induced hole mobility enhancement. We then characterized the mobility and back scattering ratio of the (110)/<111(,)> PMOS with multiple process induced stressors.
Study of quantum confinement effects on hole mobility in silicon and germanium double gate metal-oxide-semiconductor field-effect transistors
(2009-10-05)
Tang, Chun-Jung
;
Wang, Tahui
;
Chang, Chih-Sheng
;
電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Quantum confinement effects on hole mobility in silicon and germanium double gate p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) are studied by using a Monte Carlo method. Uniaxial stress and channel/substrate orientation effects are considered. Our result shows that the hole mobility in a (100)/[110] silicon well decreases with a decreasing well thickness, which is in agreement with the experimental result. The hole mobility in a germanium channel MOSFET, however, exhibits a peak in a sub-20 nm well because of the interplay between intrasubband and intersubband scatterings. (C) 2009 American Institute of Physics. [doi: 10.1063/1.3244205]