Browsing by Author "Ting, WC"

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A novel erase scheme to suppress overerasure in a scaled 2-bit nitride storage flash memory cell
(2004-09-01)
Yeh, CC
;
Wang, TH
;
Tsai, WJ
;
Lu, TC
;
Liao, YY
The cause of over-erasure in a two-bit nitride storage Flash memory cell is investigated. Extra positive charges accumulated above the n(+) unction and channel-shortening enhanced drain-induced barrier lowering effect are found to be responsible for threshold voltage (V-t) lowering in an over-erased cell. A modified erase scheme is proposed to resolve this issue. By applying a source voltage during erase, the erase speed can be well controlled for cells with different channel lengths and a wide range of program-state Vt distribution, which will reduce overerasure significantly.
A novel fully CMOS process compatible PREM for SOC applications
(2005-03-01)
Yeh, CC
;
Wang, TH
;
Tsai, WJ
;
Lu, TC
;
Liao, YY
A novel nonvolatile memory cell named programmable resistor with eraseless memory (PREM) is proposed for system on chip applications for the first time. PREM combines a novel "eraseless" algorithm and the progressive breakdown of an ultrathin oxide. No or one extra mask is needed with a standard CMOS process. Multitime programming, multilevel cell, nonvolatility, and low-voltage operation are realized. Good reliability is demonstrated based on the result of a single cell.
A novel PHINES flash memory cell with low power program/erase, small pitch, two-bits-per-cell for data storage applications
(2005-04-01)
Yeh, CC
;
Wang, TH
;
Tsai, WJ
;
Lu, TC
;
Chen, MS
A novel programming by hot-hole injection nitride electron storage (PHINES) Flash memory technology is-developed. The memory bit size of 0.046 mu m(2) is fabricated based on 0.13-mu m technology. PHINES cell uses a nitride trapping storage cell structure. Fowler-Nordheim (FN) injection is performed to raise V-t in erase while programming is done by lowering a local V-t through hand-to-hand tunneling-induced hot hole (BTBT HH) injection. Two-bits-per-cell feasibility, low-power and high-speed program/erase, good endurance and data retentivity make it a promising candidate for Flash EEPROM technology in gigabit era applications.
Characterization of programmed charge lateral distribution in a two-bit storage nitride flash memory cell by using a charge-pumping technique
(2006-01-01)
Gu, SH
;
Wang, TH
;
Lu, WP
;
Ting, WC
;
Ku, YHJ
In this paper, we use a modified charge pumping technique to characterize the programmed charge lateral distribution in a hot electron program/hot hole erase, two-bit storage nitride Flash memory cell. The stored charge distribution of each bit over the source/drain junctions can be profiled separately. Our result shows that the second programmed bit has a broader stored charge distribution than the first programmed bit. The reason is that a large channel field exists under the first programmed bit during the second bit programming. Such a large field accelerates channel electrons and causes earlier electron injection into the nitride. In addition, we find that programmed charges spread further into the channel as program/erase cycle number increases.
Lateral migration of trapped holes in a nitride storage flash memory cell and its qualification methodology
(2004-09-01)
Zous, NK
;
Lee, MY
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Tsai, WJ
;
Kuo, A
;
Huang, LT
The negative threshold voltage (V-t) shift of a nitride storage flash memory cell in the erase state will result in an increase in leakage current. By utilizing a charge pumping method, we found that trapped hole lateral migration is responsible for this V-t shift. Hole transport in nitride is characterized by monitoring gate induced drain leakage current and using a thermionic emission model. The hole emission induced V-t shift shows a linear correlation with bake time in a semi-logarithm plot and its slope depends on the bake temperature. Based on the result, an accelerated qualification method for the negative V-t drift is proposed.
Temperature effect on read current in a two-bit nitride-based trapping storage flash EEPROM cell
(2004-07-01)
Liu, MY
;
Chang, YW
;
Zous, NK
;
Yang, I
;
Lu, TC
The temperature effect on the read current of a two-bit nitride-storage Flash memory cell is investigated. In contrast to a conventional silicon-oxide-nitride-oxide (SONOS) cell with uniform Fowler-Nordheim (FN) programming, a significant high-V-T state read current increase, which results in the read window narrowing at high temperature, is observed in a channel hot electron (CHE) programmed cell. The increment of high-V-T state leakage current shows a positive correlation with program/erase threshold voltage window. Since the temperature effect is very sensitive to a locally trapped charge profile, a two-dimensional simulation with a step charge profile is employed to characterize the relationship between current increment and both charge width and charge density.