Browsing by Author "Tong, Ho-Ming"

Now showing 1 - 18 of 18

2.5D Heterogeneously Integrated Bio-Sensing Microsystem for Multi-Channel Neural-Sensing Applications
(2014-01-01)
Huang, Po-Tsang
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Chou, Lei-Chun
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Huang, Teng-Chieh
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Wu, Shang-Lin
;
Wang, Tang-Shuan
2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications
(2014-12-01)
Huang, Po-Tsang
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Wu, Shang-Lin
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Huang, Yu-Chieh
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Chou, Lei-Chun
;
Huang, Teng-Chieh
Heterogeneously integrated and miniaturized neural sensing microsystems are crucial for brain function investigation. In this paper, a 2.5D heterogeneously integrated bio-sensing microsystem with mu-probes and embedded through-silicon-via (TSVs) is presented for high-density neural sensing applications. This microsystem is composed of mu-probes with embedded TSVs, 4 dies and a silicon interposer. For capturing 16-channel neural signals, a 24 x 24 mu-probe array with embedded TSVs is fabricated on a 5 x 5 mm2 chip and bonded on the back side of the interposer. Thus, each channel contains 6 x 6 mu-probes with embedded TSVs. Additionally, the 4 dies are bonded on the front side of the interposer and designed for biopotential acquisition, feature extraction and classification via low-power analog front-end (AFE) circuits, area-power-efficient analog-to-digital converters (ADCs), configurable discrete wavelet transforms (DWTs), filters, and a MCU. An on-interposer bus (mu-SPI) is designed for transferring data on the interposer. Finally, the successful in-vivo test demonstrated the proposed 2.5D heterogeneously integrated bio-sensing microsystem. The overall power of this microsystem is only 676.3 mu W for 16-channel neural sensing.
A double-sided, single-chip integration scheme using through-silicon-via for neural sensing applications
(2015-02-01)
Chang, Chih-Wei
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Chou, Lei-Chun
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Huang, Po-Tsang
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Wu, Shang-Lin
;
Lee, Shih-Wei
We present a new double-sided, single-chip monolithic integration scheme to integrate the CMOS circuits and MEMS structures by using through-silicon-via (TSV). Neural sensing applications were chosen as the implementation example. The proposed heterogeneous device integrates standard 0.18 mu m CMOS technology, TSV and neural probe array into a compact single chip device. The neural probe array on the back-side of the chip is connected to the CMOS circuits on the front-side of the chip by using low-parasitic TSVs through the chip. Successful fabrication results and detailed characterization demonstrate the feasibility and performance of the neural probe array, TSV and readout circuitry. The fabricated device is 5x5 mm(2) in area, with 16 channels of 150 mu m-in-length neural probe array on the back-side, 200 mu m-deep TSV through the chip and CMOS circuits on the front-side. Each channel consists of a 5x6 probe array, 3x14 TSV array and a differential-difference amplifier (DDA) based analog front-end circuitry with 1.8 V supply, 21.88 mu W power consumption, 108 dB CMRR and 2.56 mu Vrms input referred noise. In-vivo long term implantation demonstrated the feasibility of presented integration scheme after 7 and 58 days of implantation. We expect the conceptual realization can be extended for higher density recording array by using the proposed method.
A TSV-Based Bio-Signal Package With mu-Probe Array
(2014-02-01)
Chou, Lei-Chun
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Lee, Shih-Wei
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Huang, Po-Tsang
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Chang, Chih-Wei
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Chiang, Cheng-Hao
Bio-signal probes providing stable observation with high quality signals are crucial for understanding how the brain works and how the neural signal transmits. Due to the weak and noisy characteristics of bio-signals, the connected interconnect length between the sensor and CMOS has significant impact on the bio-signal quality. In addition, long interconnections with wire bonding technique introduce noises and lead to bulky packaged systems. This letter presents an implantable through-silicon via (TSV) technology to connect sensors and CMOS devices located on the opposite sides of the chip for brain neural sensing applications. With the elimination of traditional wire bonding and packaging technologies, the quality of bio-signal can be greatly improved.
A TSV-Based Heterogeneous Integrated Neural-Signal Recording Device with Microprobe Array
(2014-01-01)
Chou, Lei-Chun
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Lee, Shih-Wei
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Cheng, Chuan-An
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Huang, Po-Tsang
;
Chang, Chih-Wei
Highly integrated and miniaturized neural sensing microsystems are crucial for brain function investigation and neural prostheses realization. This paper presents a TSV-based heterogeneous integrated neural-signal recording device with microprobe array. By TSV, microprobe array and CMOS circuit make connection on the opposite sides of the chip. By measurement results on electrical characteristics of devices and TSV, this recording device is ready for bio-medical applications.
Area-Power-Efficient 11-Bit SAR ADC with Delay-Line Enhanced Tuning for Neural Sensing Applications
(2013)
Huang, Teng-Chieh
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Huang, Po-Tsang
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Wu, Shang-Lin
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Chen, Kuan-Neng
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Chiou, Jin-Chern
In this paper, an area-power-efficient 11-bit hybrid analog-to-digital converter (ADC) with delay-line enhanced tuning for neural sensing applications is presented. To reduce the total amount of capacitance, this hybrid ADC is composed of a coarse tune and a fine tune by 3-bit delay-lined-based ADC and 8-bit successive approximation register (SAR) ADC, respectively. The delay-lined-based ADC is designed to detect the three most significant bits by a modified vernier structure. To relax the accuracy requirement of the coarse tune, the lifting-based searching algorithm and re-comparison procedure are proposed for the fine tune. To further achieve energy saving, split capacitor array and self-timed control are utilized in the SAR ADC. Fabricated in TSMC 0.18 mu m CMOS technology, an ENOB of 10.4-bit at 8KS/s can be achieved with only 0.6 mu W power consumption and 0.032-mm(2) area. The FoM of this ADC is 49.4fJ/conversion-step.
Energy-Efficient Configurable Discrete Wavelet Transform for Neural Sensing Applications
(2014-01-01)
Wang, Tang-Hsuan
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Huang, Po-Tsang
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Chen, Kuan-Neng
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Chiou, Jin-Chem
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Chen, Kuo-Hua
Highly integrated neural sensing microsystems are crucial to capture accurate signals for brain function investigations. In this paper, an energy-efficient configurable lifting-based discrete wavelet transform (DWT) is proposed for a high-density neural sensing microsystems to extract the features of neural signals by filtering the signals into different frequency bands. Based on the lifting-based DWT algorithm, the area and power consumption can be reduced by decreasing the computation circuits. Additionally, both the time window and mother wavelets can be adjusted via the configurable datapth. Moreover, the power-gating and clock-gating techniques are utilized to further reduce the energy consumption for the energy-limited bio-systems. The proposed configurable DWT is designed and implemented using TSMC 65nm CMOS low power process with total area of 0.11 mm(2) and power consumption of 26 mu W. Moreover, this proposed DWT is also implemented in Lattice MachXO2-1200 FPGA and integrated in a 2.5D heterogeneously integrated high-density neural-sensing microsystem with the power consumption of 211.2 mu W.
Energy-Efficient Low-Noise 16-Channel Analog-Front-End Circuit for Bio-potential Acquisition
(2014-01-01)
Wu, Shang-Lin
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Huang, Po-Tsang
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Huang, Teng-Chieh
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Chen, Kuan-Neng
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Chiou, Jin-Chern
In this paper, an energy-efficient and low-noise 16-channel analog front-end (AFE) circuitry is proposed for acquisition of electrophysiological signals. This fully integrated front-end circuit comprises two differential difference amplifiers (DDAs) and DC offset rejection components. Additionally, the DDA is designed using a double input G(m)-stage and a class-AB output for achieving high common-mode rejection ratio (CMRR), low-noise and energy efficiency. The 16-channel AFE with analog-to-digital converters (ADCs) is implemented in TSMC 0.18 mu m CMOS process. The measurement results show that the AFE can realize 60.3dB gain with only 20.67 mu W for each channel. The bandwidth of the AFE is from 2.32Hz to 6.61kHz. Furthermore, the total input referred noise and noise efficiency factor (NEF) are 0.826 mu V-rms and 2.78 only within the target frequency range of 0.1Hz to kHz, respectively.
Integrated Microprobe Array and CMOS MEMS by TSV Technology for Bio- Signal Recording Application
(2014-01-01)
Chou, Lei-Chun
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Lee, Shih-Wei
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Huang, Po-Tsang
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Chang, Chih-Wei
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Wu, Shang-Lin
Bio-signal probes that provide stable observation with high-quality signals are crucial for understanding how the brain works and how the neural signal transmits. Because bio-signals are weak and noisy, the length of the string connecting the sensor and Complementary Metal-Oxide-Semiconductor (CMOS) circuit significantly impacts biosignal quality. The collected weak signals from the sensor must pass through a series of interconnections and interfaces that introduce noise and lead to bulky packaged systems. This work uses through-silicon via (TSV) technology to connect the mu-probe array bio-sensor and CMOS circuit located on opposite sides of a chip for brain neural sensing applications. With the elimination of wire bonding and the reduction of the soldering, bio-signal quality can be significantly improved.
Investigation of ICP Parameters for Smooth TSVs and Following Cu Plating Process in 3D Integration
(2012)
Chiang, Cheng-Hao
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Hu, Yu-Chen
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Chen, Kuo-Hua
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Chiu, Chi-Tsung
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Chuang, Ching-Te
Bosch reactive ion etching is widely used for TSV formation. The micro-masking formed during etching can be successfully removed by adjusting the internal parameters during etching. The smooth high-aspect-ratio TSVs were further developed in wafer-level fabrication. Finally, a two-step etching process was developed to achieve tapered TSVs for the following Cu plating process.
Low Temperature (< 180 degrees C) Bonding for 3D Integration
(2013)
Huang, Yan-Pin
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Tzeng, Ruoh-Ning
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Chien, Yu-San
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Shy, Ming-Shaw
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Lin, Teu-Hua
Three types of bonding, including Cu-In, Sn/In-Cu, and Cu/Ti-Ti/Cu, are investigated for the application of 3D interconnects. Cu-In bonding and Sn/In-Cu bonding can form intermetallic compounds at the bonding temperature lower than 180 degrees C. In addition, for Cu/Ti-Ti/Cu bonding, Cu can be protected from oxidation by capping Ti on Cu surface before bonding. This method can further decrease bonding temperature. All bonded structures have shown excellent electrical performance and reliability characteristics. Based on bond results, these structures can be applied for low temperature bonding in 3D interconnects.
Low Temperature (< 180 degrees C) Wafer-level and Chip-level In-to-Cu and Cu-to-Cu Bonding for 3D Integration
(2013)
Chien, Yu-San
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Huang, Yan-Pin
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Tzeng, Ruoh-Ning
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Shy, Ming-Shaw
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Lin, Teu-Hua
Two bonded structures, Cu/In bonding and Cu-Cu bonding with Ti passivation, were investigated for the application of 3D interconnects. For Cu/In bonding, the bonds were achieved at 170 degrees C due to the isothermal solidification. The intermetallic compounds formed in the joint was Cu2In phase. For another case, Cu-Cu bonding with Ti passivation was successfully achieved at 180 degrees C. Application of Ti passivation can protect inner Cu from oxidation; therefore, the required bonding temperature can be decreased. Compared to direct Cu-Cu bonding, Cu/In bonding and Cu-Cu bonding with Ti passivation can be performed at low temperature, which can meet low thermal budget requirement for most devices. Besides, with the good electrical performance and reliability, these two bonded interconnects can be applied for 3D IC interconnects.
Low-Temperature Bonded Cu/In Interconnect With High Thermal Stability for 3-D Integration
(2014-04-01)
Chien, Yu-San
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Huang, Yan-Pin
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Tzeng, Ruoh-Ning
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Shy, Ming-Shaw
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Lin, Teu-Hua
Low-temperature (170 degrees C) Cu/In wafer-level and chip-level bonding for good thermal budget has been successfully developed for 3-D integration applications. For the well-bonded interconnect, Cu2In and Cu7In3 phases with high melting temperature of 388.3 degrees C and 632.2 degrees C can be formed, indicating high thermal stability. In addition, stable low specific contact resistance of bonded interfaces can be achieved with the values of approximately 0.3 x 10(-8) Omega-cm(2). In addition to exceptional electrical characteristics, the results of electrical reliability assessments including current stressing, temperature cycling, and unbiased HAST show excellent stability of Cu/In bonds without obvious deterioration. The low-temperature Cu/In bonding technology presents good bond quality and electrical performance, and possesses a great potential for future applications of 3-D interconnects.
Micro-masking Removal of TSV and Cavity during ICP Etching Using Parameter Control in 3D and MEMS Integrations
(2012)
Hu, Yu-Chen
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Chiang, Cheng-Hao
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Chen, Kuo-Hua
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Chiu, Chi-Tsung
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Chuang, Ching-Te
In this paper, a detailed examination on TSV and cavity inductive coupled plasma (ICP) etching is presented. We investigated the relation such as etching loop number, TSV etching depth and etching rate. Due to particles knocked off from the hard mask and then fallen down to the TSV and cavity bottom, micro-masking issue becomes serious after ICP etching. In addition, parameters of isotropic etching, pressure, and RF bias were studied to investigate the process of micro-masking removal.
Multi-Layer Adaptive Power Management Architecture for TSV 3DIC Applications
(2013)
Chang, Ming-Hung
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Hsieh, Wei-Chih
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Wu, Pei-Chen
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Chuang, Ching-Te
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Chen, Kuan-Neng
In this work, a multi-layer hierarchical distributed power delivery architecture for TSV 3DIC is proposed. By decoupling global and local power networks, the proposed power delivery architecture can be flexibly configured for different power requests. The decoupled power architectures can also greatly reduce the required decoupling capacitor sizes for voltage stabilization. Meanwhile, a multi-threshold CMOS switched capacitor DC-DC converter with up to 78% power efficiency is implemented in 65nm CMOS for hierarchical distributed power delivery architecture. An adaptive power management technique is presented to work in the local power network to increase the power efficiency. The proposed multi-layer hierarchical distributed power delivery architecture is also very useful for the heterogeneous integration in 3DIC chips.
Near-/Sub-V-th Process, Voltage, and Temperature (PVT) Sensors with Dynamic Voltage Selection
(2013)
Chang, Ming-Hung
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Lin, Shang-Yuan
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Wu, Pei-Chen
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Zakoretska, Olesya
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Chuang, Ching-Te
A process, voltage and temperature (PVT) sensors with dynamic voltage selection are proposed for environmental management in the ultra-low voltage dynamic voltage and frequency scaling (DVFS) system. The process and voltage (PV) sensors initially monitor the process variation. With known process information, PV sensors can real-time provide voltage variation status. The temperature sensor has six temperature sensitive ring oscillators (TSROs) generating frequency proportional to temperature. It dynamically selects the proper TSRO to convert the frequency into digital readings according to voltage status provided by PV sensors. With known process and voltage information from PV sensors, a pure temperature measurement result can be obtained. The proposed PVT sensors are designed in TSMC 65nm CMOS technology. This work can be dynamically operated over an ultra-low voltage range from 0.25V to 0.5V. Only 2.3 mu W is consumed at 0.25V. They can achieve 0.15 degrees C resolution and 50k samples/sec conversion rate.
Novel Cu-to-Cu Bonding With Ti Passivation at 180 degrees C in 3-D Integration
(2013-12-01)
Huang, Yan-Pin
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Chien, Yu-San
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Tzeng, Ruoh-Ning
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Shy, Ming-Shaw
;
Lin, Teu-Hua
A novel CMOS-compatible bond structure using Cu-to-Cu bonding with Ti passivation is demonstrated at low temperature and investigated. With the Ti protection of inner Cu, Cu bonding temperature can be reduced to 180 degrees C. In addition, excellent electrical stability against humidity and temperature cycling is achieved. Diffusion behavior and mechanism of Cu and Ti are also discussed. With excellent bond results and reliability, this bonded scheme has the potential to be applied in 3-D integration.
Through-Silicon-Via-Based Double-Side Integrated Microsystem for Neural Sensing Applications
(2013-01-01)
Chang, Chih-Wei
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Huang, Po-Tsang
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Chou, Lei-Chun
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Wu, Shang-Lin
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Lee, Shih-Wei