Browsing by Author "Tsai, Chun-Chien"

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A new pixel circuit for driving organic light emitting diodes with low temperature polycrystalline thin film transistors
(2005)
Chen, Bo-Ting
;
Kuo, Yu-Ju
;
Pai, Cheng-Chiu
;
Tsai, Chun-Chien
;
Cheng, Huang-Chung
A new active matrix organic light emitting diode (AM-OLED) pixel circuit design, based on the low-temperature polycrystalline thin-film transistors (LTPS-TFTs) is proposed and verified by SPICE simulation. The voltage-programming pixel circuit is formed by five n-type TFTs. one additional control signal, and a storage capacitor. The simulation results show that this pixel circuit has high immunity to the variation of poly-Si TFT characteristics.
A New Pixel Circuit for Driving Organic Light-Emitting Diode With Low Temperature Polycrystalline Silicon Thin-Film Transistors
(2005-09-01)
Tai, Ya-Hsiang
;
Chen, Bo-Ting
;
Kuo, Yu-Ju
;
Tsai, Chun-Chien
;
Chiang, Ko-Yu
A new pixel circuit design for active matrix organic light-emitting diode (AMOLED), based on the low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) is proposed and verified by SPICE simulation. Threshold voltage compensation pixel circuit consisting of four n-type TFTs, one p-type TFT, one additional control signal, and one storage capacitor is used to enhance display image quality. The simulation results show that this pixel circuit has high immunity to the variation of poly-Si TFT characteristics.
A novel self-aligned field induced drain polycrystalline silicon thin film transistor fabricated by using a selective side etch process
(2007)
Liao, Ta-Chuan
;
Wu, Chun-Yu
;
Chien, Feng-Tso
;
Tsai, Chun-Chien
;
Chen, Hsiu-Hsin
A novel T-shaped-gated (T-Gate) polycrystalline silicon thin-film transistor (poly-Si TFT) with vacuum gaps has been proposed and fabricated only with a simple process. The T-Gate structure is formed only by a selective undercut-etching technology of the Mo/Al bi-layers. Then, vacuum gaps are in-situ embedded in this T-Gate structure subsequent to capping the SiH4-based passivation oxide under the vacuum process chamber. Experimental results reveal that the proposed T-Gate poly-Si TFTs have excellent electrical performance, which has maximum on-off current ratio of 4.6 x 10(7), and off-state leakage current at V-GS = -10 V and V-DS = 5V of about 100 times less than that of the conventional one. These improvements are attributed to the additional undoped offset region and the vacuum gap, which reduce the maximum electric field at drain junction while the sub-gate maintains the on-current. Therefore, such a T-Gate poly-Si TFT is very suitable for the applications and manufacturing in active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diodes (AMOLEDs).
A Novel SONOS Memory With Recessed-Channel Poly-Si TFT via Excimer Laser Crystallization
(2012-04-01)
Lee, I-Che
;
Tsai, Chun-Chien
;
Kuo, Hsu-Hang
;
Yang, Po-Yu
;
Wang, Chao-Lung
A silicon-oxide-nitride-oxide-silicon memory with recessed-channel (RC) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) via excimer-laser crystallization (ELC) has been demonstrated to achieve a high mobility of similar to 400 cm(2)/V . s and a large ON/OFF current ratio of similar to 10(8). Such a high performance is because the RC poly-Si TFTs possess only one perpendicular grain boundary (GB) in the channel and the corresponding protrusion at this GB. In addition, the proposed devices also exhibited the largest memory window of 2.63 V in 10 ms with respect to 2.37 and 1.31 V for the conventional-ELC and solid-phase-crystallized ones, respectively. Since the silicon grain growth could be artificially controlled, the device-to-device uniformity could be significantly improved. Therefore, such a simple scheme is promising for applications of low-temperature poly-Si TFTs in 3-D ICs and system on panel.
A poly-Si thin-film transistor with the in situ vacuum gaps under the T-shaped-gated electrode
(2006)
Liao, Ta-Chuan
;
Wu, Chun-Yu
;
Chien, Feng-Tso
;
Tsai, Chun-Chien
;
Chen, Hsiu-Hsin
A T-shaped-gated (T-gate) poly-Si thin-film transistor (TFT) with symmetric vacuum gaps has been proposed and fabricated simply with a selective-etching technique and an in situ vacuum encapsulation. The proposed TFT has demonstrated a higher maximum on-off current ratio and superior reliability compared to the conventional TFTs. This is attributed to the resulting offset region and vacuum gap to reduce the off-state leakage current and improve the hot-carrier reliability, while the extra subgate serves to induce an inversion layer at the offset region to maintain the on current during the on state. Therefore, such a T-gate poly-Si TFT is very suitable for manufacturing and applications in active-matrix flat panel electronics. (c) 2006 The Electrochemical Society.
Characteristics of low-temperature pulse-laser-deposited (Pb,Sr)TiO3 films in metal/ferroelectric/silicon structure
(2007-01-07)
Wang, Jyh-Liang
;
Lai, Yi-Sheng
;
Lee, Trent Gwo-Yann
;
Chiou, Bi-Shiou
;
Tsai, Chun-Chien
In this study, pulsed- laser deposited ( Pb, Sr) TiO3 ( PSrT) films on p- type Si were studied at low substrate temperatures ranging from 300 to 450 degrees C for metal/ ferroelectric/ semiconductor applications. The substrate temperature strongly enhances film crystallinity without significant inter- diffusion at the PSrT/ Si interface and affects the electrical properties. As the substrate temperature increases, the films have smaller leakage currents, fewer trap states at the electrode interfaces, clockwise capacitance versus applied field hysteresis loops and larger memory windows correlated with superior crystallinity. Conversely, 300 degrees C- deposited films exhibit a small and counterclockwise loop with a positive shift of the flatband voltage, attributed to more negative trap charges within the films. However, the high substrate temperature ( 450 degrees C) may produce serious Pb - O volatilization, incurring more defects and leakage degradation. The analyses of fixed charge density and flatband voltage shift reveal the trap status and agree well with the leakage characteristic. An electron band model of the Pt/ PSrT/ Si electronic structure is proposed to explain the electrical behaviour. The excellent fatigue endurance with a small variation of memory windows (< 11%) after 1010 switching is also demonstrated.
ESD Protection Design with Latchup-Free Immunity in 120V SOI Process
(2015)
Huang, Yi-Jie
;
Ker, Ming-Dou
;
Huang, Yeh-Jen
;
Tsai, Chun-Chien
;
Jou, Yeh-Ning
Electrostatic discharge (ESD) protection with lowvoltage (LV) field-oxide devices in stacked configuration are proposed for high-voltage (HV) applications in a 0.5-mu m 120V SOI process. Stacked LV field-oxide devices with different stacking numbers have been verified in silicon chip to exhibit both of high ESD robustness and latchup-free immunity for HV applications.
Fabrication and characterization of excimer laser crystallized double-gate low-temperature poly-silicon thin film transistors
(2007)
Tsai, Chun-Chien
;
Wei, Kai-Fang
;
Lee, Yao-Jen
;
Lee, I-Che
;
Chen, Hsu-Hsin
In this letter, high-performance low-temperature poly-Silicon (LTPS) thin film transistors (TFTs) with double-gate (DG) structure and lateral silicon grains have been demonstrated by excimer laser crystallization (ELC). Therefore, the proposeed ELC DG TFTs exhibited better current-voltage characteristics as compared with the conventional solid-phase crystallized (SPC) poly-Si double-gate TFTs or conventional ELC top-gate (TG) TFTs.
Fabrication of location-controlled silicon crystal grains by combining excimer laser irradiation with nanometer-sized A-Si
(2007)
Tsai, Chun-Chien
;
Chang, Ting-Kuo
;
Chen, Hsiu-Hsin
;
Chen, Bo-Ting
;
Cheng, Huang-Chung
In this paper, location-controlled silicon crystal grains are fabricated by a novel excimer laser crystallization method. An array of 1.8-mu m-sized disk-liked grains are formed by this method, and the high-performance n-channel LTPS TFTs with field-effect-mobility reaching 308 cm(2)/Vs can be, fabricated owing to the artificially-controlled lateral grain growth. This position-manipulated silicon grains are essential to high performance and good uniformity thin film transistors.
Ferroelectricity and negative temperature coefficient of resistance in pulsed-laser-deposited (Pb, Sr) TiO(3) films
(2008-04-21)
Wang, Jyh-Liang
;
Lai, Yi-Sheng
;
Liou, Sz-Chian
;
Tsai, Chun-Chien
;
Chiou, Bi-Shiou
(Pb, Sr)TiO(3) films deposited on Pt/SiO(2)/Si substrates by pulsed-laser deposition (PLD) at 400 degrees C with oxygen pressures ranging from 50 to 200 mTorr have been investigated. The paraelectricity-to-ferroelectricity transition of films depends on the oxygen pressure during deposition. Films deposited at 200 mTorr exhibit paraelectric-like nature, whereas films deposited at lower pressures present the ferroelectric characteristic. The (Pb, Sr) TiO(3) film is found to exhibit a negative temperature coefficient of resistance (NTCR) at the measurement temperature ranging from 30 to 390 degrees C. This work demonstrates that the ferroelectricity/paraelectricity and the temperature coefficient of resistance of (Pb, Sr) TiO(3) films could be controlled by oxygen pressures during PLD.
High-Performance Bottom-Gate Poly-Si Polysilicon-Oxide-Nitride-Oxide-Silicon Thin Film Transistors Crystallized by Excimer Laser Irradiation for Two-Bit Nonvolatile Memory Applications
(2012-07-01)
Lee, I-Che
;
Kuo, Hsu-Hang
;
Tsai, Chun-Chien
;
Wang, Chao-Lung
;
Yang, Po-Yu
High-performance bottom-gate (BG) poly-Si polysilicon-oxide-nitride-oxide-silicon (SONOS) TFTs with single grain boundary perpendicular to the channel direction have been demonstrated via simple excimer-laser-crystallization (ELC) method. Under an appropriate laser irradiation energy density, the silicon grain growth started from the thicker sidewalls intrinsically caused by the bottom-gate structure and impinged in the center of the channel. Therefore, the proposed ELC BG SONOS TFTs exhibited superior transistor characteristics than the conventional solid-phase-crystallized ones, such as higher field effect mobility of 393 cm(2)/V-s and steeper subthreshold swing of 0.296 V/dec. Due to the high field effect mobility, the electron velocity, impact ionization, and conduction current density could be enhanced effectively, thus improving the memory performance. Based on this mobility-enhanced scheme, the proposed ELC BG SONOS TFTs exhibited better performance in terms of relatively large memory window, high program/erase speed, long retention time, and 2-bit operation. Such an ELC BG SONOS TFT with single-grain boundary in the channel is compatible with the conventional a-Si TFT process and therefore very promising for the embedded memory in the system-on-panel applications.
High-performance self-aligned bottom-gate low-temperature poly-silicon thin-film transistors with excimer laser crystallization
(2007-07-01)
Tsai, Chun-Chien
;
Chen, Hsu-Hsin
;
Chen, Bo-Ting
;
Cheng, Huang-Chung
;
電子工程學系及電子研究所
In this letter, high-performance bottom-gate (BG) low-temperature poly-silicon thin-film transistors (TFTs) with excimer laser crystallization have been demonstrated using self-aligned (SA) backside photolithography exposure. The grains with lateral grain size of about 0.75 mu m could be artificially grown in the channel region via the super-lateral-growth phenomenon fabricated by excimer laser irradiation. Consequently, SA-BG TFTs with the channel length of 1 pm exhibited field-effect mobility reaching 193 cm(2)/V center dot s without hydrogenation, while the mobility of the conventional non-SA-BG TFT and conventional SA top-gate one were about 17.8 and 103 cm(2)/V center dot s, respectively. Moreover, SA-BG TFTs showed higher device uniformity and wider process window owing to the homogenous lateral grains crystallized from the channel steps near the BG edges.
High-performance short-channel double-gate low-temperature polysilicon thin-film transistors using excimer laser crystallization
(2007-11-01)
Tsai, Chun-Chien
;
Wei, Kai-Fang
;
Lee, Yao-Jen
;
Chen, Hsu-Hsin
;
Wang, Jyh-Liang
In this letter, high-performance low-temperature polysilicon thin-film transistors (TFTs) with double-gate (DG) structure and controlled lateral grain growth have been demonstrated by excimer laser crystallization. Via a proper excimer laser condition, along with the a-Si step height beside the bottom gate, a superlateral growth of Si was formed in the channel length plateau. Therefore, the DG TFTs with lateral silicon grains in the channel regions exhibited better current-voltage characteristics, as compared with the conventional top-gate ones. The proposed DG TFTs (W/L = 1/1 mu m) had the field-effect mobility exceeding 550 cm(2)/V . s, an ON/OFF current ratio that is higher than 10(8), superior short-channel characteristics, and higher current drivability. In addition, the device-to-device uniformity could be improved since grain growth could be artificially controlled by the spatial plateau structure.
High-performance top and bottom double-gate low-temperature poly-silicon thin film transistors fabricated by excimer laser crystallization
(2008-03-01)
Tsai, Chun-Chien
;
Lee, Yao-Jen
;
Wang, Jyh-Liang
;
Wei, Kai-Fang
;
Lee, I-Che
In this work, high-performance low-temperature poly-silicon (LTPS) thin film transistors (TFTs) with double-gate (DG) structure and lateral grain growth have been demonstrated by excimer laser crystallization (ELC). Therefore, the DG TFTs with lateral silicon grains in the channel regions exhibited better current-voltage characteristics as compared with the conventional solid-phase crystallized (SPC) poly-Si double-gate TFTs or conventional ELC top-gate (TG) TFTs. The proposed ELC DG TFTs (W/L = 1.5/1.5 mu m) had the field-effect-mobility exceeding 400 cm(2)/V s, on/off current ratio higher than 10(8), superior short-channel characteristics and higher current drivability. (c) 2007 Elsevier Ltd. All rights reserved.
High-performance vertically stacked bottom-gate and top-gate polycrystalline silicon thin-film transistors for three-dimensional integrated circuits
(2012-11-01)
Lee, I-Che
;
Tsai, Tsung-Che
;
Tsai, Chun-Chien
;
Yang, Po-Yu
;
Wang, Chao-Lung
The three-dimensional CMOS inverter with top-gate (TG) poly-Si thin film transistors (TFTs) vertically stacked on the bottom-gate (BC) poly-Si TFTs have been proposed to achieve high-performance characteristics via excimer laser crystallization (ELC) for the first time. Under an appropriate laser irradiation energy density, the silicon grain growth could be controlled from the sidewalls of the bottom-gate structure and thus the high-quality laterally grown poly-Si film with single perpendicular grain boundary in the channel would be formed for the BC TFTs. In addition, a simple ELC method was also utilized to the top-layered poly-Si film for TG TFTs as compared with solid-state-crystallized (SPC) ones. As a result, the field-effect mobilities of the proposed n-type BC and p-type TG TFTs could be significantly increased to be 390 and 131 cm(2)/V s, respectively, in contrast to 32.3 and 14.7 cm(2)/V s for the SPC ones, accordingly. Furthermore, such three-dimensional (3-D) TFT have also been employed to demonstrate the inverter devices and is suitable for future 3-D ICs as well as system-on-panel applications. (c) 2012 Elsevier Ltd. All rights reserved.
Impact of Guard Ring Layout on the Stacked Low-Voltage PMOS for High-Voltage ESD Protection
(2015)
Liao, Seian-Feng
;
Tang, Kai-Neng
;
Ker, Ming-Dou
;
Yeh, Jia-Rong
;
Chiou, Hwa-Chyi
Electrostatic discharge (ESD) protection and latchup prevention are two important reliability issues to the CMOS integrated circuits, especially in high-voltage (HV) applications. In this work, the stacked low-voltage (LV) PMOS devices have been successfully verified in a 0.5-mu m HV process to provide high ESD level with high holding voltage for HV applications. In addition, the guard-ring layout on the stacked LV PMOS devices was further investigated in silicon chip to get high ESD robustness and latchup-free immunity for HV applications.
Investigation of source-follower type analog buffer using low temperature poly-Si TFTs
(2007-03-01)
Chen, Bo-Ting
;
Tai, Ya-Hsiang
;
Wei, Ying-Jyun
;
Wei, Kai-Fang
;
Tsai, Chun-Chien
A new source follower circuit using low-temperature polycrystalline silicon thin film transistors (LTPS-TFTs) as analog buffer for the integrated data driver circuit of active matrix liquid crystal displays (AMLCDs) and active matrix light emitting diodes (AMOLEDs) is proposed and measured. Threshold voltage compensation circuit with two n-type thin film transistors, a capacitor, and four switches structure is used to enhance image quality for the display. The threshold voltage difference of driving TFTs and the unsaturated of output voltage are eliminated in this circuit. An active load is added and a calibration operation is applied to study the effects on the source follower circuit, the transistor operation mode region is also discussed. The proposed circuit is capable of minimizing the variation from both the signal timing and the device characteristics through the simulation and measured results. (C) 2007 Elsevier Ltd. All rights reserved.
Low temperature polycrystalline silicon thin film transistors fabricated by amorphous silicon spacer structure with pre-patterned TEOS oxide layer
(2005)
Cheng, Huang-Chung
;
Tsai, Chun-Chien
;
Lu, Jian-Hao
;
Chang, Ting-Kuo
;
Lin, Ching-Wei
In this paper, location-controlled grain growth with a-Si spacer structure was fabricated. Consequently, High-performance poly-Si TFTs with field-effect mobility exceeding 367 cm(2)/V-s and high device uniformity have been fabricated. The excellent electrical characteristics is attributed to large grain and grain boundary elimination in the channel region.
Memory characteristics of laser-crystallized polycrystalline-silicon silicon-oxide-nitride-oxide-silicon thin-film transistor with location-controlled grain boundary perpendicular to the channel
(2012-06-11)
Lee, I-Che
;
Tsai, Chun-Chien
;
Kuo, Hsu-Hang
;
Yang, Po-Yu
;
Wang, Chao-Lung
An excimer-laser-crystallized polycrystalline-silicon silicon-oxide-nitride-oxide-silicon thin-film transistor with recessed-channel structure has been designed to achieve only one grain boundary with a protrusion perpendicular to the channel for investigating the grain boundary location effects on the memory characteristics. After programming, the devices demonstrated better memory characteristics as the grain boundary was allocated near the source junction. In contrast, the memory characteristics were degraded when the grain boundary was located near the drain junction. The phenomenon was explained by the 2-D device simulation and the energy band diagrams. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4724314]
New analog buffer circuit using low temperature polycrystalline thin film transistors for active matrix displays
(2005)
Tai, Ya-Hsiang
;
Chen, Bo-Ting
;
Kuo, Yu-Ju
;
Wei, Ying-Jyun
;
Pai, Cheng-Chiu
Two types new simple source follower circuit using low-temperature polycrystalline silicon thin film transistors (LTPS-TFTs) as analogue buffer for the integrated data driver circuit of active matrix liquid crystal displays (AMLCDs) and active matrix light emitting diodes (AMOLEDs) are proposed. Analogue buffer designs are discussed and verified by SPICE simulation results.