Browsing by Author "Tsai, Han-Ting"

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Design of Wide-IF-Band CMOS Mixer with LO Multiplier
(2013)
Tsai, Han-Ting
;
Tseng, Pei-Ling
;
Chang, Che-Wei
;
Hu, Robert
;
Jou, Christina F.
This paper reports the development of K-band wide-IF-band CMOS mixer with LO multiplier suitable for wideband applications. To achieve such broad bandwidth, several design techniques-such as current-reuse differential-pair with LC resonance circuit, and simultaneous in-band gain peaking and off-band gain tailoring-have been analyzed and employed. The on-wafer measurement of this 17.4-26.1GHz TSMC 0.18 mu m CMOS mixer with LO doubler shows a -1dB conversion gain, 11dB noise figure, -6dBm input-referred 1dB compression point, 40dB RF-IF isolation, and 45dB LO-IF isolation at 8.7GHz. The chip size is 1400 x 1300 mu m(2).
Microwave and Millimeter-Wave CMOS Frequency Doubler and Tripler Designs
(2014-01-01)
Wu, Kun-Long
;
Tsai, Han-Ting
;
Tseng, Pei-Ling
;
Hu, Robert
;
Jou, Christina F.
This manuscript describes our 17.4GHz 0.18 mu m-CMOS doubler and 77GHz 65nm-CMOS tripler designs. For the doubler, attention has been made on effectively suppressing the fundamental, third and forth harmonics using LLC filtering networks and balun. As for the tripler, the unwanted second-order harmonic can be suppressed through the use of large source impedance on the differential pair while the fundamental signal leakage is removed by an embedded notch filter; therefore, the intended third-harmonic output is almost 40dB larger than all the other spurious signals. The tripler chip size is 700x940um, and it consumes 93mW under 1.2V bias; the 3dB bandwidth for output is 9GHz.