Browsing by Author "Tsai, JM"

Now showing 1 - 6 of 6

A multicasting solution for ATM video applications
(1997-08-01)
Tsai, JM
;
Fang, HH
;
Lee, CY
;
交大名義發表
;
電子工程學系及電子研究所
This paper presents a multicasting solution for shared-buffer ATM switch, The cell duplicating function is performed by a one-to-many modified demur circuit, A shared multicast server is used to translate input multicast cells to find destination ports and corresponding routing information, By using link-list based ring structure, the multicast server can provide high speed (5 ns to search entry in 256-entry block in 0.8-mu m CMOS process) and cascadable multicast translating function, In addition, the channel complexity of multipoint-to-multipoint multicast applications can be reduced to N channels per N users. The shared-buffer controller is modified by adding controlling and scheduling functions for multicasting queues to process the multicast feature. Finally with the aid of the quality of service (QoS) management, this proposed solution provides multi-QoS for multicast cells to meet the needs of various video applications.
A multicasting solution for ATM video applications
(1997-01-01)
Tsai, JM
;
Fang, HH
;
Ju, CC
;
Lee, CY
;
電子工程學系及電子研究所
This paper presents a multicasting solution for shared-buffer ATM switch. The cell duplicating function is performed by a one-to-many modified demux circuit. A shared multicast server is used to translate input multicast cells to find destination ports and corresponding routing information. By using link-list based ring structure, the multicast server can provide high speed (5ns for search entry in 256-entry block in 0.8 mu m CMOS process) and cascadable multicast translating function. In addition, the channel complexity of multipoint-to-multipoint multicast applications can be reduced to N channels per N users. The shared-buffer controller is modified by adding controlling and scheduling functions for multicasting queues to process the multicast feature.
A multicasting solution for ATM video applications
(1997-08-01)
Tsai, JM
;
Fang, HH
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a multicasting solution for shared-buffer ATM switch, The cell duplicating function is performed by a one-to-many modified demur circuit, A shared multicast server is used to translate input multicast cells to find destination ports and corresponding routing information, By using link-list based ring structure, the multicast server can provide high speed (5 ns to search entry in 256-entry block in 0.8-mu m CMOS process) and cascadable multicast translating function, In addition, the channel complexity of multipoint-to-multipoint multicast applications can be reduced to N channels per N users. The shared-buffer controller is modified by adding controlling and scheduling functions for multicasting queues to process the multicast feature. Finally with the aid of the quality of service (QoS) management, this proposed solution provides multi-QoS for multicast cells to meet the needs of various video applications.
A shift register architecture for high-speed data sorting
(1995-12-01)
Lee, CY
;
Tsai, JM
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a shift-register architecture or SRA, for data sorting applications. The operations performed by the proposed architecture are (1) shift right, (2) shift left, (3) load, and (4) initialize. Sorting operations, such as insert and delete, can be realized by the combination of these 4 basic operations. The architecture is very regular and mainly composed of two basic cells, sort-cell and compare-cell. The latter is designed to generate control signals orchestrating the operation of sort cells which contain the sorted input sequences. Experimental results show that a single chip solution can achieve real-time performance based on 1.2 mu m CMOS double-metal technology.
Novel architecture for ATM QoS management
(1997-12-01)
Tsai, JM
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel architecture and an enhanced approach to a flexible, starvation-free ATM QoS managing function is proposed. To meet the stringent timing constraint of the delay QoSs, both high-speed sorter and subtracter are exploited to sort the priority value as well as to process the priority value. The subtractive policy is used to prevent starvation and to assign the priority of each output queue. In addition, to prevent underflow of priority value and to process the empty queue situation, both renormalisation circuit and empty flag are exploited to perform the normalisation function. Simulation results show that the throughput of the enhanced architecture is more than 50 M output requests per second (21.2 Gbit/s for ATM cells) by using a 1.2 mu m CMOS process. The proposed architecture can be cascadable, making it very suitable for complex QoS management.
Novel architecture for ATM QoS management
(1997-12-01)
Tsai, JM
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel architecture and an enhanced approach to a flexible, starvation-free ATM QoS managing function is proposed. To meet the stringent timing constraint of the delay QoSs, both high-speed sorter and subtracter are exploited to sort the priority value as well as to process the priority value. The subtractive policy is used to prevent starvation and to assign the priority of each output queue. In addition, to prevent underflow of priority value and to process the empty queue situation, both renormalisation circuit and empty flag are exploited to perform the normalisation function. Simulation results show that the throughput of the enhanced architecture is more than 50 M output requests per second (21.2 Gbit/s for ATM cells) by using a 1.2 mu m CMOS process. The proposed architecture can be cascadable, making it very suitable for complex QoS management.