Browsing by Author "Tsai, Ming-Chien"

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A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing
(2012-06-01)
Tu, Ming-Hsien
;
Lin, Jihi-Yu
;
Tsai, Ming-Chien
;
Lu, Chien-Yu
;
Lin, Yuh-Jiun
This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure. The disturb-free feature facilitates bit-inter-leaving architecture, which can reduce multiple-bit upsets in a single word and enhance soft error immunity by employing Error Checking and Correction (ECC) technique. The proposed 9T SRAM cell is demonstrated by a 72 Kb SRAM macro with a Negative Bit-Line (NBL) Write-assist and an adaptive Read operation timing tracing circuit implemented in 65 nm low-leakage CMOS technology. Measured full Read and Write functionality is error free with V-DD down to 0.35 V (similar to 0.15 V lower than the threshold voltage) with 229 KHz frequency and 4.05 mu W power. Data is held down to 0.275 V with 2.29 mu W Standby power. The minimum energy per operation is 4.5 pJ at 0.5 V. The 72 Kb SRAM macro has wide operation range from 1.2 V down to 0.35 V, with operating frequency of around 200 MHz for V-DD around/above 1.0 V.
An All-Digital Bit Transistor Characterization Scheme for CMOS 6T SRAM Array
(2012)
Lin, Geng-Cing
;
Wang, Shao-Cheng
;
Lin, Yi-Wei
;
Tsai, Ming-Chien
;
Chuang, Ching-Te
We present an all-digital bit transistor characterization scheme for CMOS 6T SRAM array. The scheme employs an on-chip operational amplifier feedback loop to measure the individual threshold voltage (VTH) of 6T SRAM bit cell transistors (holding PMOS, pull-down NMOS, and access NMOS) in SRAM cell array environment. The measured voltage is converted to frequency with dual VCO and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. A 512Kb test chip is implemented in 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations indicate that the accuracy of the VTH measurement scheme is about 2-7mV at TT corner across temperature range from 85 degrees C to -45 degrees C, and post-layout simulations show the resolution of the digital read-out scheme is < 0.2mV per bit. Measured VTH distributions agree well with Monte Carlo simulation results.
Asymmetrical Write-Assist for Single-Ended SRAM Operation
(2009)
Lin, Jihi-Yu
;
Tu, Ming-Hsien
;
Tsai, Ming-Chien
;
Jou, Shyh-Jye
;
Chuang, Ching-Te
In this paper, asymmetrical Write-assist cell virtual ground biasing and positive feedback sensing keeper schemes are proposed to improve the Read Static Noise Margin (RSNM), Write Margin (WM), and operation speed of a single-ended Read/Write 8T SRAM cell. A 4Kbit SRAM implemented in 90nm CMOS technology achieves 1uW/bit average power consumption at 6MHz, V(min) of 410mV at 6MHz, and 234MHz maximum operation frequency at 600mV.
Design and Implementation of Dynamic Word-Line Pulse Write Margin Monitor for SRAM
(2012)
Wang, Shao-Cheng
;
Lin, Geng-Cing
;
Lin, Yi-Wei
;
Tsai, Ming-Chien
;
Chiu, Yi-Wei
We present an all-digital monitor structure to measure the Write Margin (WM) with dynamic Word-Line (WL) pulse for standard CMOS 6T SRAM. Ring oscillator and frequency divider based structures are used to generate wide range WL pulses (150ps similar to 32ns) with resolution of 50ps. The bit-line voltage is then successively stepped down for dynamic Write Margin characterization under given word-line pulse width. An improved Skitter based structure is employed to measure the WL pulse width with resolution of 10 similar to 20ps. Implementation of a 256Kb test chip in UMC 55nm Standard Performance (SP) CMOS technology is described.
Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist
(2010-12-01)
Tu, Ming-Hsien
;
Lin, Jihi-Yu
;
Tsai, Ming-Chien
;
Jou, Shyh-Jye
;
Chuang, Ching-Te
In this paper, asymmetrical Write-assist cell virtual ground biasing scheme and positive feedback sensing keeper schemes are proposed to improve the read static noise margin (RSNM), write margin (WM), and operation speed of a single-ended read/write 8 T SRAM cell. A 4 Kbit SRAM test chip is implemented in 90 nm CMOS technology. The test chip measurement results show that at 0.2 V V(DD), an operation frequency of 6.0 MHz can be achieved with power consumption of 10.4 mu W.