Asymmetrical Write-Assist for Single-Ended SRAM Operation

Abstract

In this paper, asymmetrical Write-assist cell virtual ground biasing and positive feedback sensing keeper schemes are proposed to improve the Read Static Noise Margin (RSNM), Write Margin (WM), and operation speed of a single-ended Read/Write 8T SRAM cell. A 4Kbit SRAM implemented in 90nm CMOS technology achieves 1uW/bit average power consumption at 6MHz, V(min) of 410mV at 6MHz, and 234MHz maximum operation frequency at 600mV.