Asymmetrical Write-Assist for Single-Ended SRAM Operation

dc.citation.epage	104	en_US
dc.citation.spage	101	en_US
dc.contributor.author	Lin, Jihi-Yu	en_US
dc.contributor.author	Tu, Ming-Hsien	en_US
dc.contributor.author	Tsai, Ming-Chien	en_US
dc.contributor.author	Jou, Shyh-Jye	en_US
dc.contributor.author	Chuang, Ching-Te	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2014-12-08T15:19:40Z
dc.date.available	2014-12-08T15:19:40Z
dc.date.issued	2009	en_US
dc.description.abstract	In this paper, asymmetrical Write-assist cell virtual ground biasing and positive feedback sensing keeper schemes are proposed to improve the Read Static Noise Margin (RSNM), Write Margin (WM), and operation speed of a single-ended Read/Write 8T SRAM cell. A 4Kbit SRAM implemented in 90nm CMOS technology achieves 1uW/bit average power consumption at 6MHz, V(min) of 410mV at 6MHz, and 234MHz maximum operation frequency at 600mV.	en_US
dc.identifier.isbn	978-1-4244-5220-0	en_US
dc.identifier.journal	IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/13978
dc.identifier.wosnumber	WOS:000277503200020
dc.language.iso	en_US	en_US
dc.title	Asymmetrical Write-Assist for Single-Ended SRAM Operation	en_US
dc.type	Article	en_US

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