Browsing by Author "Tsai, Tsung-Hsien"

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A 0.1-3GHz Cell-Based Fractional-N All Digital Phase-Locked Loop Using Delta Sigma Noise-Shaped Phase Detector
(2013-01-01)
Liu, Yao-Chia
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Chen, Wei-Zen
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Chou, Mao-Hsuan
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Tsai, Tsung-Hsien
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Lee, Yen-Wei
A 0.1-3 GHz, cell-based, fractional-N ADPLL with Delta Sigma noise-shaped phase detector is presented. By dithering the reference phase and quantization phase error through an additional feedback path, linear phase detection and zero stabilization are accomplished without resort to sophisticated time to digital converter (TDC). The measured rms jitter from a 3GHz carrier is 1.9 ps with a multiplication factor of 60. Implemented in TSMC 40nm general purpose superb CMOS technology, the chip size is 280um x 240um.
Algorithm and Architecture of Disparity Estimation With Mini-Census Adaptive Support Weight
(2010-06-01)
Chang, Nelson Yen-Chung
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Tsai, Tsung-Hsien
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Hsu, Bo-Hsiung
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Chen, Yi-Chun
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Chang, Tian-Sheuan
High-performance real-time stereo vision system is crucial to various stereo vision applications, such as robotics, autonomous vehicles, multiview video coding, freeview TV, and 3-D video conferencing. In this paper, we proposed a high-performance hardware-friendly disparity estimation algorithm called mini-census adaptive support weight (MCADSW) and also proposed its corresponding real-time very large scale integration (VLSI) architecture. To make the proposed MCADSW algorithm hardware-friendly, we proposed simplification techniques such as using mini-census, removing proximity weight, using YUV color representation, using Manhattan color distance, and using scaled-and-truncate weight approximation. After applied these simplifications, the MCADSW algorithm was not only hardware-friendly, but was also 1.63 times faster. In the corresponding realtime VLSI architecture, we proposed partial column reuse and access reduction with expanded window to significantly reduce the bandwidth requirement. The proposed architecture was implemented using United Microelectronics Corporation (UMC) 90 nm complementary metal-oxide-semiconductor technology and can achieve a disparity estimation frame rate of 42 frames/s for common intermediate format size images when clocked at 95 MHz. The synthesized gate-count and memory size is 563k and 21.3 kB, respectively.
Data reuse analysis of local stereo matching
(2008)
Tsai, Tsung-Hsien
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Chang, Nelson Yen-Chung
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
External memory bandwidth and internal memory size have been major bottlenecks in designing VLSI architecture for real-time stereo matching hardware because of large amount of pixel data and disparity range. To address these bottlenecks, this work explores the impact of data reuse on disparity-order and pixel-order along with the partial column reuse (PCR) and vertically expanded row reuse (VERR) techniques we proposed. The analysis suggest that a disparity-order reuse with both PCR and VERR techniques is suitable for low memory cost and low external bandwidth design, whereas the pixel-order reuse with both techniques is more suitable for low computation resource requirement.
Dynamic Flow Aggregation in SDNs for Application-aware Routing
(2016)
Tsai, Tsung-Hsien
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Wang, Kuochen
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Chao, Tzu-Yu
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資訊工程學系
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網路工程研究所
The software defined network (SDN) presents a good opportunity to realize application-aware routing by offering programmability for the network. Due to limited sizes of ternary content addressable memories (TCAMs) in SDN switches, flow aggregation is needed to resolve the flow table overflow problem. We propose bit & subset weaving to relieve the problem which utilizes instruction slicing to produce an instruction-independent partition and applies the bit and subset weaving to merge flow entries in each subset of a partition. Comparing with the Fast Flow Table Aggregation (FFTA) scheme [7], the average compression ratio (the average flow aggregation time) of the proposed bit & subset weaving is better (smaller) than that of FFTA.
Real-time DSP implementation on local stereo matching
(2007)
Chang, Nelson
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Lin, Ting-Min
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Tsai, Tsung-Hsien
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Tseng, Yu-Cheng
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Chang, Tian-Sheuan
Real-time DSP stereo matching solution has been important to various applications relying on stereo vision. We proposed a 4x5 jigsaw matching template and the dual-block parallel processing technique to enhance VLIW DSP stereo matcher's performance. The 4x5 jigsaw template improves the matching quality by 1% compared with regular 4x5 block template while consuming the same amount of memory access bandwidth. Along with the benefit of the jigsaw template, the dual-block parallel processing technique, which doubles the throughput, is possible to be implemented for DSP. Together with instruction scheduling and operation pipelining, our DSP stereo matcher can achieve 50 FPS of 16 disparity levels for a 384x288 stereo image pair. Both quantitative and qualitative stereo matching results are provided at the end of this work.