Browsing by Author "Tseng, WD"

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Fault coverage and defect level estimation models for partially testable MCMs
(2000-04-01)
Tseng, WD
;
Wang, K
;
資訊工程學系
;
Department of Computer Science
The authors propose a simple and efficient mathematical model for designers to estimate fault coverage for partially testable multichip modules (MCMs). This model shows a relation between fault covet-age, lest methodology, and the fraction and distribution of design for testability (DFT) dies in MCMs. Experimental results show that the proposed model can efficiently predict the fault coverage of a partially testable MCM with less than 5% deviation. An automatic DFT dies deployment algorithm, based on the genetic algorithm and the model is proposed to help designers to obtain a fault coverage as close to the upper bound of fault coverage as possible. Two defect level estimation models, which relate fault coverage and manufacturing yield for measuring the test quality of MCMs under equiprobable and non-equiprobable faults, respectively, are also formulated and analysed to support the effectiveness of the model.
Fault coverage estimation model for partially testable multichip modules
(1997)
Tseng, WD
;
Wang, KC
;
資訊工程學系
;
Department of Computer Science
This paper proposes a simple and efficient model for designers to estimate fault coverage for partially testable MCMs. This model relates fault coverage, test methodology, and the ratio and distribution of DFT dies (dies with design for testability features) in an MCM. Experimental results show that our model can efficiently predict the fault coverage of a partially testable MCM with less than 5% deviation. In addition, the upper bound far fault coverage is also analyzed to guide the designers to know when to stop the effort in planning the use of DFT dies. Two defect level estimation models which relate fault coverage and manufacturing yield for measuring the test quality of MCMs under equiprobable and nonequiprobable faults, respectively, are also presented and evaluated.
Fuzzy-based circuit partitioning in built-in current testing
(1996)
Tseng, WD
;
Wang, KC
;
交大名義發表
;
資訊工程學系
;
National Chiao Tung University
Partitioning a digital circuit into modules before implementing on a single chip is key to balancing between test cost and test correctness of built-in current testing (BICT). Most partitioning methods use statistic analysis to find the threshold value and then to determine the size of a module. These methods are rigid and inflexible since IDDQ testing requires the measurement of an analog quantity rather than a digital signal. In this paper, we propose a fuzzy-based approach which provides a soft threshold to determine the module size for BICT partitioning. Evaluation results show that our design approach indeed provides a feasible way to exploit the design space of BICT partitioning.
Fuzzy-based CMOS circuit partitioning in built-in current testing
(1999-03-01)
Tseng, WD
;
Wang, KC
;
資訊工程學系
;
Department of Computer Science
We propose a fuzzy-based approach which pro,ides a soft threshold to determine the module size for CMOS circuit partitioning in built-in current testing (BICT). Experimental results show that our design approach indeed provides a feasible way to exploit the design space of BICT partitioning in comparison with other approaches with a fixed threshold, and a better module size can thus he determined to reflect a change of circuit properties.
Testable design and testing of MCMs based on multifrequency scan
(1996)
Tseng, WD
;
Wang, KC
;
資訊工程學系
;
Department of Computer Science