Browsing by Author "Tseng, Yu-Cheng"

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A 124 Mpixels/s VLSI Design for Histogram-Based Joint Bilateral Filtering
(2011-11-01)
Tseng, Yu-Cheng
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Hsu, Po-Hsiung
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents an efficient and scalable design for histogram-based bilateral filtering (BF) and joint BF (JBF) by memory reduction methods and architecture design techniques to solve the problems of high memory cost, high computational complexity, high bandwidth, and large range table. The presented memory reduction methods exploit the progressive computing characteristics to reduce the memory cost to 0.003%-0.020%, as compared with the original approach. Furthermore, the architecture design techniques adopt range domain parallelism and take advantage of the computing order and the numerical properties to solve the complexity, bandwidth, and range-table problems. The example design with a 90-nm complementary metal-oxide-semiconductor process can deliver the throughput to 124 Mpixels/s with 356-K gate counts and 23-KB on-chip memory.
A Parametric Window Design for OBMC with Variable Block Size Motion Estimates
(2009)
Chen, Yi-Wen
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Wang, Tse-Wei
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Tseng, Yu-Cheng
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Peng, Wen-Hsiao
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Lee, Suh-Yin
This paper addresses the problem of adapting overlapped block motion compensation (OBMC) windows for use with variable blocksize motion estimates. We tackle the problem by using a parametric window design, which expresses, based on a statistical motion model, the optimal weights as a function of the distances between the predicted pixel and its nearby block centers. The formula enables both prediction weights and prediction order to be adapted on a pixel-by-pixel basis. Extensive experiments have been conducted using JM 12.4. Compared with conventional block motion compensation, our scheme shows a bitrate saving of 18%, (5% on average) while maintaining the same or even higher PSNR (0.1 dB). It also provides a competitive advantage to variable block size motion compensation. Additionally, a hybrid of the two techniques achieves a further bitrate reduction of 13%. The result, nevertheless, provides only a lower bound on what is achievable since both motion estimation and mode decision were accomplished without considering OBMC. Further improvement is expected by incorporating iterative methods.
Analysis of Color Space and Similarity Measure Impact on Stereo Block Matching
(2008)
Chang, Nelson Yen-Chung
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Tseng, Yu-Cheng
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Chang, Tian Sheuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The impact of color space and similarity measure on complexity, speed, and performance of stereo matching is especially important to applications adopting stereo vision. This work analyzed the complexity of several most commonly considered color space and similarity measure. In addition, the execution speed and performance of color space and similarity measure combination arc also compared on the same basis. The comparison result suggests that the Y-only rank provides the best combination under speed and performance trade-off.
Architecture Design of Belief Propagation for Real-Time Disparity Estimation
(2010-11-01)
Tseng, Yu-Cheng
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Belief propagation based algorithms perform best in disparity estimation but suffer from high computational complexity and storage, especially in message passing. This paper proposes an efficient architecture design with three techniques to solve the problems. For the memory storage, we propose the spinning-message and the sliding-bipartite node plane that can reduce memory cost to 1.2% for image-scale algorithms and 23.4% for block-scale algorithms, when compared to the traditional approach. For the logic complexity, we propose a buffer-free processing element architecture that has 3.6 times hardware efficiency of the previous work. The three proposed techniques could be applied to various belief propagation based algorithms to save significant hardware cost as well as approach real-time speed.
Architecture Design of Belief Propagation for Real-Time Disparity Estimation
(2010-11-01)
Tseng, Yu-Cheng
;
Chang, Tian-Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Belief propagation based algorithms perform best in disparity estimation but suffer from high computational complexity and storage, especially in message passing. This paper proposes an efficient architecture design with three techniques to solve the problems. For the memory storage, we propose the spinning-message and the sliding-bipartite node plane that can reduce memory cost to 1.2% for image-scale algorithms and 23.4% for block-scale algorithms, when compared to the traditional approach. For the logic complexity, we propose a buffer-free processing element architecture that has 3.6 times hardware efficiency of the previous work. The three proposed techniques could be applied to various belief propagation based algorithms to save significant hardware cost as well as approach real-time speed.
Block-based Belief Propagation With In-place Message Updating for Stereo Vision
(2008)
Tseng, Yu-Cheng
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Chang, Nelson Yen-Chung
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The large message-memory size has been a major design issue in belief propagation for stereo matching methods. To reduce its size, we proposed an in-place message updating approach which stores new messages into expired ones. Thus, this approach only needs one message memory and a small temporary message memory. Further combining with block based belief propagation, the final architecture only needs 172KB memory and can reduce internal memory size by 40% when compared with traditional ping-pong buffer approach.
FAST DISPARITY ESTIMATION FOR 3DTV APPLICATIONS
(2012)
Tseng, Yu-Cheng
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The depth estimation reference software (DERS) algorithm developed by the MPEG 3-D Video Coding could produce high-quality disparity maps for 3DTV applications but suffers from high computational complexity due to its complicated graph-cut optimization. Therefore, this paper proposed a new fast disparity estimation algorithm that could significantly reduce the computational complexity by the downsampled matching cost method. To address the temporal consistency in videos, this paper proposed the no-motion registration for the foreground copy artifact and the still-edge preservation for the flicker artifact. In addition, the occlusion problem is also solved in the proposed algorithm. The experimental results show that our algorithm could generate comparable disparity maps to the DERS algorithm, and only takes 10.8% of its execution time.
Information preserving color transformation for protanopia and deuteranopia
(2007-10-01)
Huang, Ha-Bin
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Tseng, Yu-Cheng
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Wu, Se-In
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Wang, Sheng-Jyh
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電子工程學系及電子研究所
In this letter, we proposed a new recoloring method for people with protanopic and deuteranopic color deficiencies. We present a color transformation that aims to preserve the color information in the original images while maintaining the recolored images as natural as possible. Two error functions are introduced and combined together to form an objective function using the Lagrange multiplier with a user-specified parameter A. This objective function is then minimized to obtain the optimal settings. Experimental results show that the proposed method can yield more comprehensible images for color-deficient viewers while maintaining the naturalness of the recolored images for standard viewers.
Low Memory Cost Bilateral Filtering Using Stripe-based Sliding Integral Histogram
(2010)
Hsu, Po-Hsiung
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Tseng, Yu-Cheng
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Bilateral filter can well smooth images while preserving edges, and thus has been widely used in various applications. However, it needs significant memory cost due to a whole image storage. This paper develops three methods to significantly reduce the memory cost. The runtime updating method (RUM) discards unnecessary data in runtime. The stripe-based integral histogram method (SBM) divides image into vertical image-stripes. The sliding origin method (SOM) sliding moves the origin of integration region to achieve the most memory reduction. The final result shows that the proposed approach only needs 24Kbits memory, which saves 99.993% of memory cost for smoothing a VGA-sized image with 30-fps speed, when compared to the previous optimized constant time integral histogram approach.
Low memory cost block-based belief propagation for stereo correspondence
(2007)
Tseng, Yu-Cheng
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Chang, Nelson
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Chang, Tian-Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The typical belief propagation has good accuracy for stereo correspondence but suffers from large run-time memory cost. In this paper, we propose a block-based belief propagation algorithm for stereo correspondence that partitions an image into regular blocks for optimization. With independently partitioned blocks, the required memory size could be reduced significantly by 99% with slightly degraded performance with a 3202 block size when compared to original one. Besides, such blocks are also suitable for parallel hardware implementation. Experimental results using Middlebury stereo test bed demonstrate the performance of the proposed method.
Low-Memory Cost Belief Propagation Architecture for Disparity Estimation
(2009)
Tseng, Yu-Cheng
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Chang, Nelson Yen-Chung
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In disparity estimation, belief propagation can deliver better disparity quality than other algorithms but suffer from large storage cost, especially at the message update processing. To reduce the storage cost, this paper proposes low-memory cost architectures for the message update PE to satisfy the real-time application. We propose four architectures which are post-normalization, shadow buffer, no memory, and no memory+double PE architectures. Compared to the previous design, the proposed no memory+double PE architecture can save 28% of the hardware cost at most for 320x240@30fps and 64 disparity levels.
Real-time DSP implementation on local stereo matching
(2007)
Chang, Nelson
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Lin, Ting-Min
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Tsai, Tsung-Hsien
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Tseng, Yu-Cheng
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Chang, Tian-Sheuan
Real-time DSP stereo matching solution has been important to various applications relying on stereo vision. We proposed a 4x5 jigsaw matching template and the dual-block parallel processing technique to enhance VLIW DSP stereo matcher's performance. The 4x5 jigsaw template improves the matching quality by 1% compared with regular 4x5 block template while consuming the same amount of memory access bandwidth. Along with the benefit of the jigsaw template, the dual-block parallel processing technique, which doubles the throughput, is possible to be implemented for DSP. Together with instruction scheduling and operation pipelining, our DSP stereo matcher can achieve 50 FPS of 16 disparity levels for a 384x288 stereo image pair. Both quantitative and qualitative stereo matching results are provided at the end of this work.
Stereoscopic Images Generation with Directional Gaussian Filter
(2010)
Horng, Ying-Rung
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Tseng, Yu-Cheng
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The depth-based image rendering (DIBR) uses monoscopic image with its corresponding depth map to generate stereoscopic images for 3DTV. The main difficulty in the DIBR is that holes appear in the stereoscopic images because of the occlusion between objects. However, the previous depth smoothing methods to reduce holes usually destroy the perceived depth quality or the perceived naturalness. This paper proposed a new depth smoothing method to solve these problems by applying a new directional Gaussian filter guided by edge direction in the hole-flag area iteratively. The subjective evaluation results show that our proposed method can generate better stereoscopic images with good perceived depth quality as well as perceived naturalness.
VLSI Architecture for Real-Time HD1080p View Synthesis Engine
(2011-09-01)
Horng, Ying-Rung
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Tseng, Yu-Cheng
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents a real-time HD1080p view synthesis engine based on the reference algorithm from 3-D video coding team by solving high computational complexity and high memory cost problems. For the computational complexity, we propose the bilinear interpolation to simplify the hole filling process, and the Z scaling method with floating-point format to reduce the cost of homography calculation. For the memory cost, we propose the frame-level pipelining to reduce the requirement of warped depth maps, and the column-order warping method to remove the Z-buffer in occlusion handling. With the 90nm complementary metal-oxide-semiconductor technology, our view synthesis engine can archive the throughput of 32.4 f/s for HD1080p videos with the gate count of 268.5K and the internal memory of 69.4 kbytes. The experimental result shows our implementation has the similar synthesis quality as the original reference algorithm.