Browsing by Author "Tu, Yung-Yi"

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An EWOD-based micro diluter with high flexibility on dilution ratio
(2017-08-01)
Wang, Ying-Bin
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Huang, Jun-Hao
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Lee, Meng-Shiue
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Huang, Cheng-Yeh
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Huang, Cheng-Sheng
Dilution is a common procedure in biological and chemical analyses to perform tests at different concentrations. In previously reported micro diluters, although they could provide a wide dilution range, only limited dilution ratios were demonstrated, i.e. low flexibility in dilution ratio. Here, a droplet-based micro diluter with high flexibility on dilution ratio is proposed, fabricated, and tested. Through combination of five different electrode sizes using electrowetting-on-dielectric (EWOD) technique, the proposed micro diluter can provide 49 dilution ratios at dilution range from 1/2 to 1/50. Experimental results verify that different dilution ratios can be successfully generated, even at the most difficult low concentration range. Comparing to the design with equal electrode size in conventional EWOD-based microfluidic chip, the proposed design with unequal electrode sizes can reduce the operation steps to achieve high flexibility on dilution ratios efficiently.
Contact resistance reduction on layered MoS2 by Ar plasma pre-treatment
(2016)
Ho, Yen-Teng
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Chu, Yung-Ching
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Jong, Chao An
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Chen, Hung-Yi
;
Lin, Meng-Wei
The effect of resistance (Rc) reduction of Ti/Au contact on MoS2 by ICP Ar plasma pretreatment is presented. The lowest Rc of 1.72 ohm-cm was achieved with the ICP treatment condition of 50W (ICP) /2W (chuck) for 10 sec. Compared with the contact without treatment (19.6 ohm-cm), the Rc improves over 10 times, demonstrating the advantage of Ar plasma pre-treatment on MoS2 contact.
Direct growth of a 40 nm InAs thin film on a GaAs/Ge heterostructure by metalorganic chemical vapor deposition
(2014-09-01)
Yu, Hung-Wei
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Wang, Tsun-Ming
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Nguyen, Hong-Quan
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Wong, Yuen-Yee
;
Tu, Yung-Yi
In this paper, the authors directly grew an InAs thin film (40 nm) by metalorganic chemical vapor deposition on GaAs/Ge substrates by using flow-rate modulation epitaxy with an appropriate V/III ratio. The growth of a high-quality InAs thin film with periodic 90 degrees misfit dislocations was related to a uniform monolayer In atom distribution at the InAs/GaAs interface. The In monolayer effectively minimized the difference between surface energy and strain energy, producing a stable interface during material growth. The authors also found that a tightly controlled V/III ratio can improve the quality of the InAs islands on the GaAs/Ge heterostructures, though it is not the key factor in InAs thin-film growth. (C) 2014 American Vacuum Society.
Effects of initial GaN growth mode on the material and electrical properties of AlGaN/GaN high-electron-mobility transistors
(2014-09-01)
Wong, Yuen-Yee
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Chang, Edward Yi
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Huang, Wei-Ching
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Lin, Yueh-Chin
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Tu, Yung-Yi
AlGaN/GaN high-electron-mobility transistors (HEMTs) with different initial GaN growth modes were prepared on AIN/sapphire substrates. Secondary ion mass spectroscopy and Hall effect measurements confirmed that a highly conductive n-type region was generated at the GaN/AIN buffer interface during the three-dimensional to two-dimensional (3D-2D) growth mode transition. This n-type region was created by oxygen impurity incorporation during the 3D-2D growth mode transition, and its thickness increased with the transition time. The existence of this n-type conduction path not only changed the material properties but also degraded the device performance of HEMTs. (C) 2014 The Japan Society of Applied Physics
Investigation of electrical and thermal properties of multiple AlGaN/GaN high-electron-mobility transistors flip-chip packaged in parallel for power electronics
(2015-03-01)
Tsai, Szu-Ping
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Hsu, Heng-Tung
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Tu, Yung-Yi
;
Chang, Edward Yi
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材料科學與工程學系
This paper demonstrates, for the first time, the potential of using flip-chip packaging to connect multiple AlGaN/GaN high-electron-mobility transistors (HEMTs) in parallel for application in power electronics. The electrical and thermal properties of both the bare and the packaged devices were experimentally investigated via pulsed current-voltage (I-V) measurements. Compared to the bare die, less than one-fifth the thermal resistance (R-th), triple the output current, and one-third the on-resistance (R-on) with temperature insensibility were observed when three transistors were connected in parallel through flip-chip packaging. Superior performance such as this makes flip-chip packaging a potential technology for high power GaN electronic applications. (C) 2015 The Japan Society of Applied Physics
Layered MoS2 grown on c-sapphire by pulsed laser deposition
(2015-03-01)
Ho, Yen-Teng
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Ma, Chun-Hao
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Luong, Tien-Tung
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Wei, Lin-Lung
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Yen, Tzu-Chun
Layered growth of molybdenum disulphide (MoS2) was successfully achieved by pulsed laser deposition (PLD) method on c-plane sapphire substrate. Growth of monolayer to a few monolayer MoS2, dependent on the pulsed number of excimer laser in PLD is demonstrated, indicating the promising controllability of layer growth. Among the samples with various pulse number deposition, the frequency difference (A1gE12g) in Raman analysis of the 70 pulse sample is estimated as 20.11 cm(1), suggesting a monolayer MoS2 was obtained. Two-dimensional (2D) layer growth of MoS2 is confirmed by the streaky reflection high energy electron diffraction (RHEED) patterns during growth and the cross-sectional view of transmission electron microscopy (TEM). The in-plane relationship, (0006) sapphire//(0002) MoS2 and inline image sapphire//inline imageMoS(2) is determined. The results imply that PLD is suitable for layered MoS2 growth. Additionally, the oxide states of Mo 3d core level spectra of PLD grown MoS2, analysed by X-ray photoelectron spectroscopy (XPS), can be effectively reduced by adopting a post sulfurization process. (C) 2015 WILEY-VCH Verlag GmbH &Co. KGaA, Weinheim
Low resistance copper-based ohmic contact for AlGaN/GaN high electron mobility transistors
(2013-10-07)
Wong, Yuen-Yee
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Chen, Yu-Kong
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Maa, Jer-Shen
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Yu, Hung-Wei
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Tu, Yung-Yi
Ti/Al/Ni/Cu ohmic contact for AlGaN/GaN structure has been fabricated. The Ni layer played an important role in achieving low specific contact resistance (r(c)), smooth morphology, and excellent edge acuity. With a 50-angstrom Ni layer, a r(c) of 1.35 x 10(-6) Omega-cm(2) and a root-mean-square roughness of 7.65 nm have been realized. The characterization results indicated that no evidence of Cu diffusion into the semiconductor layers. The formation of Al-Cu and Ti-Cu alloys might have confined the Cu within the ohmic metal. In the absence of gold, the surface roughening caused by Au-Al alloy in conventional Ti/Al/Ni/Au structure was also prevented. (C) 2013 AIP Publishing LLC.
Performance Enhancement of Flip-Chip Packaged AlGaN/GaN HEMTs Using Active-Region Bumps-Induced Piezoelectric Effect
(2014-07-01)
Tsai, Szu-Ping
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Hsu, Heng-Tung
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Chiang, Che-Yang
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Tu, Yung-Yi
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Chang, Chia-Hua
We experimentally investigated the impact of different bump patterns on the output electrical characteristics of flip-chip (FC) bonded AlGaN/GaN high-electron mobility transistors in this letter. The bump patterns were designed and intended to provide different levels of tensile stress due to the mismatch in the coefficient of thermal expansion between the materials. After FC packaging, a maximum increase of 4.3% in saturation current was achieved compared with the bare die when proper arrangement of the bumps in active region was designed. In other words, a 17% improvement has been observed on the optimized bump pattern over the conventional bump pattern. To the best of our knowledge, this is the first letter that investigates the piezoelectric effect induced by FC bumps leading to the enhancement in device characteristics after packaging.
Performance Enhancement of Flip-Chip Packaged AlGaN/GaN HEMTs Using Active-Region Bumps-Induced Piezoelectric Effect
(2014-07-01)
Tsai, Szu-Ping
;
Hsu, Heng-Tung
;
Chiang, Che-Yang
;
Tu, Yung-Yi
;
Chang, Chia-Hua
We experimentally investigated the impact of different bump patterns on the output electrical characteristics of flip-chip (FC) bonded AlGaN/GaN high-electron mobility transistors in this letter. The bump patterns were designed and intended to provide different levels of tensile stress due to the mismatch in the coefficient of thermal expansion between the materials. After FC packaging, a maximum increase of 4.3% in saturation current was achieved compared with the bare die when proper arrangement of the bumps in active region was designed. In other words, a 17% improvement has been observed on the optimized bump pattern over the conventional bump pattern. To the best of our knowledge, this is the first letter that investigates the piezoelectric effect induced by FC bumps leading to the enhancement in device characteristics after packaging.
POST SULFURIZATION EFFECT ON THE MOS2 GROWN BY PULSED LASER DEPOSITION
(2016)
Ho, Yen-Teng
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Yen, Tzu-Chun
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Luong, Tien-Tung
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Wei, Lin-Lung
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Tu, Yung-Yi
Two inches size with high quality layered growth of MoS2 was achieved by PLD on c-plane sapphire substrate. 2-3 monolayer MoS2 was obtained within 2 inches wafer estimated from Raman analysis and confirmed by cross-sectional view of TEM. Additionally, the oxide states of Mo 3d core level spectra of MoS2, analyzed by XPS, can be effectively reduced by adopting a post sulfurization process in H2S. The post process also improve the photoluminescence (PL) of MoS2 as well as the electrical characteristic of MoS2 FET due to elimination the Mo oxide in the grown film.
Structural and electrical properties analysis of InAlGaN/GaN heterostructures grown at elevated temperatures by MOCVD
(2018-11-01)
Lumbantoruan, Franky
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Zheng, Xia-Xi
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Huang, Jian-Hao
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Huang, Ren-Yao
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Mangasa, Firman
We report the effects of the growth temperature on the structural and electrical properties of the InAlGaN/GaN heterostructures grown on c-plane sapphire substrates. X-ray Photoelectron Spectroscopy and Atomic Force Microscopy measurements results indicate that the InAlGaN layer properties is strongly dependent on the growth temperature. It is observed that the Gallium incorporation increases with the increase of the growth temperature. Meanwhile, the surface roughness decreases from 0.49 nm to 0.34 nm with the increase of growth temperature. The variation of structural properties, composition and surface morphology influences the transport properties of the InAlGaN/GaN heterostructures. High 2DEG electron density, low sheet resistance and good C-V response with a steep slope for InAlGaN/GaN HEMT were achieved at an optimized growth temperature window between 900 degrees C and 950 degrees C.
Synthesis of Wafer-Scale WSe2 by WOx Selenization on SiO2 / Si Substrates
(2016)
Chu, Yung-Ching
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Jong, Chao-An
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Ho, Yen-Teng
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Zhang, Ming
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Chien, Po-Yen
Scalable synthesis of thin tungsten diselenide (WSe2) films on 4-inch silicon substrate with 80 nm silicon dioxide (SiO2) is demonstrated. Cross-sectional transmission electron microscopy (TEM) reveals good control of WSe2 layers. Raman spectroscopy confirms high quality crystal of WSe2 is achieved. Back-gated field-effect transistors (FETs) fabricated on these thin films exhibit p-channel characteristics with a good on/off current ratio larger than 1.2 x 10(2).
The Effect of the Thickness of the Low Temperature AlN Nucleation Layer on the Material Properties of GaN Grown on a Double-Step AlN Buffer Layer by the MOCVD Method
(2016-02)
Huang, Wei-Ching
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Chu, Chung-Ming
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Hsieh, Chi-Feng
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Wong, Yuen-Yee
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Chen, Kai-Wei
The influence of low-temperature AlN (LT-AlN) nucleation layer thickness on the material properties of the GaN layer grown on the double-step AlN layer is investigated. When GaN was grown without the LT-AlN nucleation layer, the GaN layer has low sheet resistance of 464 ohm/sq and the surface was decorated with pitted region. On the other hand, when a LT-AlN layer with a thickness of 5 nm was inserted, a GaN layer with sheet resistance higher than 10(6) ohm/sq was achieved. This thin nucleation layer also improved the GaN morphology, suppressed inversion domain formation, and reduced oxygen impurity incorporation. However, the surface morphology and quality of the GaN crystal were severely degraded when the LT-AlN thickness was increased to 10 nm due to the formation of disorientated grains in the LT-AlN layer.
WAFER SIZE MOS2 WITH FEW MONOLAYER SYNTHESIZED BY H2S SULFURIZATION
(2017-01-01)
Ho, Yen-Teng
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Chu, Yung-Ching
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Wei, Lin-Lung
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Luong, Tien-Tung
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Lin, Chih-Chien
Wafer sized, high quality continuous fihns would be a key demand for MoS2 implemented in circuit application. In this study, the growth of few monolayer Mo-S2 on 4 inches SiO2/Si substrate were demonstrated. The MoS2 thin films were synthesized by sulfurized in a furnace from the ultra-thin MoO3 starting materials by using H2S. The obtained MoS2 thin film examined by Raman analysis and Photoluminescence (PL), shows the semiconductor nature with direct transition peaks of 1.86 eV and 1.99 eV. The 4 5 monolayer of MoS2 with thickness around 2.6 nm is confirmed by cross-sectional view of transmission electron microscopy (TEM). Additionally, the DC characteristics of MoS2 MOSFETs exhibit at least 2 order in on/off current ratio, demonstrating the feasibility for circuit application.