Browsing by Author "Wang, HCH"

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A novel transient characterization technique to investigate trap properties in HfSiON gate dielectric MOSFETs - From single electron emission to PBTI recovery transient
(2006-05-01)
Wang, TH
;
Chan, CT
;
Tang, CJ
;
Tsai, CW
;
Wang, HCH
A positive bias temperature instability (PBTI) recovery transient technique is presented to investigate trap properties in HfSiON as high-k gate dielectric in nMOSFETs. Both large and small-area nMOSFETs are characterized. In a large-area device, the post-PBTI drain current exhibits a recovery transient and follows logarithmic time dependence. In a small-area device, individual trapped electron emission from HfSiON gate dielectric, which is manifested by a staircase-like drain current evolution with time, is observed during recovery. By measuring the temperature and gate voltage dependence of trapped electron emission times, the physical mechanism for PBTI recovery is developed. An analytical model based on thermally assisted tunneling can successfully reproduce measured transient characteristics. In addition, HfSiON trap properties, such as trap density and activation energy, are characterized by this method.
Arsenic/phosphorus LDD optimization by taking advantage of phosphorus transient enhanced diffusion for high voltage input/output CMOS devices
(2002-01-01)
Wang, HCH
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Wang, CC
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Diaz, CH
;
Liew, BK
;
Sun, JYC
Optimization of a LDD doping profile to enhance hot carrier resistance in 3.3 V input/output CMOS devices has been performed by utilizing phosphorus transient enhanced diffusion (TED). Hot carrier effects in hybrid arsenic/phosphorus LDD nMOSFET's with and without TED are characterized comprehensively. Our result shows that the substrate current in a nMOSFET with phosphorus TED can be substantially reduced as compared to the one without TED. The reason is that the TED effect can yield a more graded n(-) LDD doping profile and thus a smaller lateral electric field. Further improvement of hot carrier reliability can be achieved by optimizing arsenic implant energy. Secondary ion mass spectrometry analysis for TED effect and two-dimensional (2-D) device simulation for electric field
Continuous and precise work function adjustment for integratable dual metal gate CMOS technology using Hf-Mo binary alloys
(2005-06-01)
Li, TL
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Hu, CH
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Ho, WL
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Wang, HCH
;
Chang, CY
We demonstrate for the first time a continuous and almost linear work function adjustment between 3.93 and 4.93 eV using HfxMo(1-x) binary alloys deposited by co-sputtering. In view of the process integration, dual work function metal gate technology using Mo and HfxMo(1-x) formed by metal intermixing was proposed. Work function values were verified to be a function of the thickness ratio and accurate work function adjustment can be possible. Furthermore, one can be allowed to get around the thermal stability issue by choosing an appropriate total metal thickness corresponding to the thermal budget subsequent to gate deposition, since the thermal budget required for metal intermixing depends on the total metal thickness.
Hot carrier reliability improvement by utilizing phosphorus transient enhanced diffusion for input/output devices of deep submicron CMOS technology
(2000-12-01)
Wang, HCH
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Diaz, CH
;
Liew, BK
;
Sun, JYC
;
Wang, TH
This letter presents a deep submicron CMOS process that takes advantage of phosphorus transient enhanced diffusion (TED) to improve the hot carrier reliability of 3.3 V input/output transistors, Arsenic/phosphorus LDI) nMOSFETs with and without TED are fabricated. The TED effects on a LDD junction profile, device substrate current and transconductance degradation are evaluated, Substantial substrate current reduction and hot carrier lifetime improvement for the input/output devices are attained due to a more graded n(-) LDD doping profile by taking advantage of phosphorus TED.
Interface induced uphill diffusion of boron: An effective approach for ultrashallow junction
(2001-02-01)
Wang, HCH
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Wang, CC
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Chang, CS
;
Wang, TH
;
Griffin, PB
This paper investigates anomalous diffusion behavior for ultra low energy implants in the extension or tip of PMOS devices. Transient enhanced diffusion (TED) is minimal at these low energies, since excess interstitials are very close to the surface, Instead, interface induced uphill diffusion is found, for the first time, to dominate during low temperature thermal cycles. The interface pile-up dynamics can be taken advantage of to produce shallower junctions and improve short channel effect control in PMOS devices, Attempts to minimize TED before spacer deposition by inclusion of extra RTA. anneals are shown to be detrimental to forming boron ultra shallow junctions.
Novel dual-metal gate technology using Mo-MoSix combination
(2006-06-01)
Li, TL
;
Ho, WL
;
Chen, HB
;
Wang, HCH
;
Chang, CY
A novel dual-metal gate technology that uses a combination of Mo-MoSix gate electrodes is proposed. An amorphous-Si/Mo stack was fabricated as a gate electrode for the n-channel device. It was thermally annealed to form MoSix. Pure Mo served as the gate electrode for the p-channel device. The work functions of MoSix and pure Mo gates on SiO2 are 4.38 and 4.94 eV, respectively, which are appropriate for devices with advanced transistor structures. The small increase in the work function (< 20 meV) and the negligible equivalent oxide thickness variation (< 0.08 nm) after rapid thermal annealing at 950 degrees C for 30 s also demonstrate the excellent thermal stabilities of Mo and MoSix on SiO2. Additional arsenic ion implantation prior to silicidation was demonstrated further to lower the work function of MoSix to 4.07 eV. This approach for modulating the work function makes the proposed combination of Mo-MoSix gate electrodes appropriate for conventional bulk devices. The developed dual-metal-gate technology on HfO2 gate dielectric was also evaluated. The effective work functions of pure Mo and undoped MoSix gates on HfO2 are 4.89 and 4.34 eV, respectively. A considerable work-function shift was observed on the high-k. gate dielectric. The effect of arsenic preimplantation upon the work function of the metal silicide on HfO2 was also demonstrated, even though the range of modulation was a little reduced.
Positive bias and temperature stress induced two-stage drain current degradation in HfSiON nMOSFET's
(2005)
Chan, CT
;
Tang, CJ
;
Wang, T
;
Wang, HCH
;
Tang, DD
Positive bias and temperature (PBTI) stress induced drain current degradation in HfSiON gate dielectric nMOSFETs is investigated by using a transient measurement technique. The degradation exhibits two stages, featuring different degradation rate and stress temperature dependence. The drain current degradation in the first stage is attributed to the charging of pre-existing high-k dielectric traps while the degradation in the second stage is mainly due to additional high-k trap creation. Process effect on high-k trap growth is evaluated.
Single-electron emission of traps in HfSiON as high-k gate dielectric for MOSFETs
(2005)
Chan, CT
;
Tang, CJ
;
Kuo, CH
;
Ma, HC
;
Tsai, CW
A novel method for characterizing MOSFETs with HfSiON high-k gate dielectric is demonstrated for the first time by direct measurement of single-electron de-trapping. Individual high-k trapped electron emission is recorded, which is manifested by the step-like evolution of channel current. The physical path of electron de-trapping can be identified from the emission time of such single-electron de-trapping. The dependence of charge emission time on gate voltage and temperature is measured. An analytical model based on thermally assisted tunneling can predict the emission time behavior, trap activation energy, trap density, and total available traps in high-k gate dielectric.