Browsing by Author "Wang, Jer-Chyi"

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A Fluorographene-Based Synaptic Transistor
(2019-08-13)
Liu, Bo
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Hong, Ming-Chun
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Sahoo, Mamina
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Ong, Bin Leong
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Tok, Eng Soon
Exploring brain-inspired synaptic devices has recently become a new focus of research in nanoelectronic communities. In this emerging field, incorporating 2D materials into three-terminal synaptic transistors has brought various advantages. However, achieving a stable and long-term weight-modulation in these synaptic transistors, which are typically based on interface charge storage, is still a challenge due to the nature of their spontaneous relaxation. The application of an atomically thin fluorographene layer into the synaptic junction region suppresses this issue and improves the efficiency, tunability, and symmetry of the synaptic plasticity as well as establishing a stable weight-regulation paradigm. These unique properties can be attributed to the dipolar rotation of C-F in fluorographene. To obtain a better physical understanding, a vacancy-dependent C-F dipolar rotation model is proposed and supported by hysteresis analysis and density functional theory calculations. As proposed and demonstrated, the unique fluorographene-based synaptic transistor may be a promising building block for constructing efficient neuromorphic computing hardware.
A highly reliable multi-level and 2-bit/cell operation of wrapped-select-gate (WSG) SONOS memory with optimized ONO thickness
(2007)
Wu, Woei-Cherng
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Chao, Tien-Sheng
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Peng, Wu-Chin
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Yang, Wen-Luh
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Wang, Jer-Chyi
High-performance wrapped-select-gate (WSG) SONOS (silicon-oxide-nitride-silicon) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism with different ONO thickness in WSG-SONOS memory was well investigated. The different programming efficiency of the WSG-SONOS memory with different ONO thickness can be explained by the lateral electrical field extracted from the simulation. Furthermore, multi-level storage is easily obtained and well V-th distribution is also presented. High program/erase speed (10us/5ms) and low programming current (3.5uA) are performed to achieve the multi-level operation with excellent gate and drain disturbance, second-bit effect, data retention and endurance.
Carrier transportation mechanism of the TaN/HfO(2)/IL/Si structure with silicon surface fluorine implantation
(2008-07-01)
Wu, Woei Cherng
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Lai, Chao-Sung
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Wang, Tzu-Ming
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Wang, Jer-Chyi
;
Hsu, Chih Wei
In this paper, the current transportation mechanism of HfO(2) gate dielectrics with a TaN metal gate and silicon surface fluorine implantation is investigated. Based on the experimental results of the temperature dependence of gate leakage current and Fowler-Nordheim tunneling characteristics at 77 K, we have extracted the current transport mechanisms and energy band diagrams for TaN/HfO(2)/IL/Si structures with fluorine incorporation, respectively. In particular, we have obtained the following physical quantities: 1) fluorinated and as-deposited interfacial layer (IL)/Si barrier heights (or conduction band offsets) at 3.2 and 2.7 eV; 2) TaN/fluorinated and as-deposited HfO(2) barrier heights at 2.6 and 1.9 eV; and 3) effective trapping levels at 1.25 eV (under both gate and substrate injections) below the HIM conduction band and at 1.04 eV (under gate injection) and 1.11 eV (under substrate injection) below the HfO(2) conduction band, which contributes to Frenkel-Poole conduction.
Dimensionally anisotropic graphene with high mobility and a high on-off ratio in a three-terminal RRAM device
(2020-06-01)
Liu, Bo
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Tai, Han Hsiang
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Liang, Hanyuan
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Zheng, En-Yan
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Sahoo, Mamina
In the past decade, graphene has aroused worldwide academic passion in the electronics community, due to its unique two dimensional lattice structure and high mobility properties. Meanwhile, the utilization of graphene for next-generation nano-electronic materials is still under debate due to its intrinsic zero band gap nature. To meet the requirement of logic applications, diversified academic attempts have been carried out to modify its intrinsic band structure, such as doping, bilayer stacking, nano-patterning, or heterostructures. In this work, a tailor made strategy for graphene is proposed and experimentally demonstrated: a dimensionally anisotropic graphene based three terminal resistive random-access memory (RRAM). This device could be operated in two modes, which realized not only high carrier mobility (10(3) cm(2) V-1 s(-1)) and low gate leakage in field effect mode, but also a high on-off ratio (10(7)) and ultra-low off state current (1 pA) in resistive switching mode. This device also exhibits high reliability in logic data storage: long retention up to 8000 s, endurance of 400 DC operation cycles, and read immunity up to 1 million cycles. To guarantee the dimensional uniformity and high quality of the graphene, surface polishing and passivation techniques were carried out on Cu foil before graphene CVD synthesis. As demonstrated in this study, the current work paves the way for graphene toward practical logic and memory applications with high performance and low steady state power consumption.
Fluorinated HfO2 Gate Dielectrics Engineering for CMOS by pre- and post-CF4 Plasma Passivation
(2008)
Wu, Woei-Chemg
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Lai, Chao-Sung
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Lee, Shih-Ching
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Ma, Ming-Wen
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Chao, Tien-Sheng
In this paper, we demonstrate TaN/Fluorinated HfO2 CMOS devices, focusing on symmetry and asymmetry fluorine incorporation at top or bottom HfO2 interfaces. 16% permittivity enhancement, 65% and 91% mobility increases for electron and hole, respectively, under high electric field was achieved. Reliability of n- and p-MOSFET was improved 3 orders and 8% for GIDL and hot carrier immunity, respectively. A physical model of shallow and deep trapping level affected by fluorine was proposed to explain the NBTI and PBTI improvements.
Highly reliable multilevel and 2-bit/cell operation of wrapped select gate (WSG) SONOS memory
(2007-03-01)
Wu, Woei-Cherng
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Chao, Tien-Sheng
;
Peng, Wu-Chin
;
Yang, Wen-Luh
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Wang, Jer-Chyi
In this letter, high-performance and reliable wrapped select gate (WSG) polysilicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multilevel and 2-bit/cell operation have been successfully demonstrated. The multilevel storage is easily obtained with fast program/erase speed (10 mu s/5 ms) and low programming current (3.5 mu A) for our WSG SONOS by a source-side injection. Besides the excellent reliability properties of our multilevel WSG-SONOS memory including unconsidered gate and drain disturbance, long charge retention (> 150 degrees C) and good endurance (> 10(4)) are also presented. This novel WSG-SONOS memory with a multilevel and 2-bit/cell operation can be used in future high-density and high-performance memory application.
Performance and interface characterization for contact etch stop layer-strained nMOSFET with HfO2 gate dielectrics under pulsed-IV measurement
(2008)
Wu, Woei-Cherng
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Chao, Tien-Sheng
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Chiu, Te-Hsin
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Wang, Jer-Chyi
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Lai, Chao-Sung
In this paper, high-performance contact etching stop layer (CESL)-strained n-metal-oxide-semiconductor field effect transistor (nMOSFET) with HfO2 gate dielectrics has been successfully demonstrated. The effects of the CESL layer to the high-k without trapping behaviors are investigated by the pulse current-voltage (IV) technique for the first time. It is found that a roughly 55 and 60% increase of mobility and I-ON, respectively, can be achieved for the 300 nm CESL HfO2 nMOSFET using pulsed-IV measurement. Furthermore, a superior HfO2/Si interface for CESL devices is observed, demonstrated by an obvious interface state density reduction (6 x 10(11)-9 x 10(10) cm(-2)).
Performance enhancement for strained HfO(2) nMOSFET with contact etch stop layer (CESL) under pulsed-IV measurement
(2007)
Wu, Woei-Cherng
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Chao, Tien-Sheng
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Chiu, Te-Hsin
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Wang, Jer-Chyi
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Lai, Chao-Sung
High-performance CESL strained nMOSFET with HfO(2) gate dielectrics has been successfully demonstrated in this work. It is found that, the transconductance (g(m)) and driving current (I(on)) of the nMOSFETs increase 70% and 90%, respectively, of the increase of devices with a 300 nm capping nitride layer. A superior HfO(2)/Si interface for CESL-devices is observed, demonstrated by an obvious interface state density reduction (6.56x10(11) to 9.85x10(10) cm(-2)). Further, a roughly 50% and 60% increase of g(m) and I(on), respectively, can be achieved for the 300 nm SiN-capped HfO(2) nMOSFET without considering charge trapping under pulsed-IV measurement.
Positive Bias Temperature Instability (PBTI) Characteristics of Contact-Etch-Stop-Layer-Induced Local-Tensile-Strained HfO(2) nMOSFET
(2008-12-01)
Wu, Woei-Cherng
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Chao, Tien-Sheng
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Chiu, Te-Hsin
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Wang, Jer-Chyi
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Lai, Chao-Sung
The positive bias temperature instability (PBTI) characteristics of contact-etch-stop-layer (CESL)-strained HfO(2) nMOSFET are thoroughly investigated. For the first time, the effects of CESL on an HfO(2) dielectric are investigated for PBTI characteristics. A roughly 50% reduction Of V(TH) shift can be achieved for the 300-nm CESL HfO(2) nMOSFET after 1000-s PBTI stressing without obvious HfO(2)/Si interface degradation, as demonstrated by the negligible charge pumping current increase (< 4%). In addition, the HfO(2) film of CESL devices has a deeper trapping level (0.83 eV), indicating that most of the shallow traps (0.75 eV) in as-deposited HfO(2) film can be eliminated for CESL devices.
Positive Bias Temperature Instability (PBTI) Characteristics of Contact-Etch-Stop-Layer-Induced Local-Tensile-Strained HfO2 nMOSFET
(2008-12-01)
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Chiu, Te-Hsin
;
Wang, Jer-Chyi
;
Lai, Chao-Sung
The positive bias temperature instability (PBTI) characteristics of contact-etch-stop-layer (CESL)-strained HfO2 nMOSFET are thoroughly investigated. For the first time, the effects of CESL on an HfO2 dielectric are investigated for PBTI characteristics. A roughly 50% reduction Of V-TH shift can be achieved for the 300-nm CESL HfO2 nMOSFET after 1000-s PBTI stressing without obvious HfO2/Si interface degradation, as demonstrated by the negligible charge pumping current increase (< 4%). In addition, the HfO2 film of CESL devices has a deeper trapping level (0.83 eV), indicating that most of the shallow traps (0.75 eV) in as-deposited HfO2 film can be eliminated for CESL devices.
Programmable Synaptic Metaplasticity and below Femtojoule Spiking Energy Realized in Graphene-Based Neuromorphic Memristor
(2018-06-20)
Liu, Bo
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Liu, Zhiwei
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Chiu, In-Shiang
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Di, MengFu
;
Wu, YongRen
Memristors with rich interior dynamics of ion migration are promising for mimicking various biological synaptic functions in neuromorphic hardware systems. A graphene-based memristor shows an extremely low energy consumption of less than a femtojoule per spike, by taking advantage of weak surface van der Waals interaction of graphene. The device also shows an intriguing programmable metaplasticity property in which the synaptic plasticity depends on the history of the stimuli and yet allows rapid reconfiguration via an immediate stimulus. This graphene-based memristor could be a promising building block toward designing highly versatile and extremely energy efficient neuromorphic computing systems.