Browsing by Author "Wang, Jingli"

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Dielectric Engineering of a Boron Nitride/Hafnium Oxide Heterostructure for High-Performance 2D Field Effect Transistors
(2016-03-09)
Zou, Xuming
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Huang, Chun-Wei
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Wang, Lifeng
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Yin, Long-Jing
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Li, Wenqing
A unique design of a hexagonal boron nitride (h-BN)/HfO2 dielectric heterostructure stack is demonstrated, with few-layer h-BN to alleviate the surface optical phonon scattering, followed by high-kappa HfO2 deposition to suppress Coulombic impurity scattering so that high-performance top-gated two-dimensional semiconductor transistors are achieved. Furthermore, this dielectric stack can also be extended to GaN-based transistors to enhance their performance.
High Mobility MoS2 Transistor with Low Schottky Barrier Contact by Using Atomic Thick h-BN as a Tunneling Layer
(2016-10-05)
Wang, Jingli
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Yao, Qian
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Huang, Chun-Wei
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Zou, Xuming
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Liao, Lei
High-performance MoS2 transistors are developed using atomic hexagonal boron nitride as a tunneling layer to reduce the Schottky barrier and achieve low contact resistance between metal and MoS2. Benefiting from the ultrathin tunneling layer within 0.6 nm, the Schottky barrier is significantly reduced from 158 to 31 meV with small tunneling resistance.
Interface Engineering for High-Performance Top-Gated MoS2 Field-Effect Transistors
(2014-09-24)
Zou, Xuming
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Wang, Jingli
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Chiu, Chung-Hua
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Wu, Yun
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Xiao, Xiangheng
Experimental evidence of the optimized interface engineering effects in MoS2 transistors is demonstrated. The MoS2/Y2O3/HfO2 stack offers excellent interface control. Results show that HfO2 layer can be scaled down to 9 nm, yet achieving a near-ideal sub-threshold slope (65 mv/dec) and the highest saturation current (526 mu A/mu m) of any MoS2 transistor reported to date.
Low Interface Trap Densities and Enhanced Performance of AlGaN/GaNMOS High-Electron Mobility Transistors Using Thermal Oxidized Y2O3 Interlayer
(2015-12-01)
Liao, Chongnan
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Zou, Xuming
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Huang, Chun-Wei
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Wang, Jingli
;
Zhang, Kai
AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs) with Y2O3 interlayer have been investigated to improve the interface quality. With the HfO2/Y2O3 stack gate dielectrics, the devices show a saturated drain current density of up to similar to 943 mA/mm. Meanwhile, the pulsed I-d-V-g measurement indicates interface traps are as low as 5.2 x 10(11) cm(-2), and the pulsed-IV measurement exhibits great resistance to current collapse. Furthermore, the devices also present good reliability under negative bias stress. Therefore, the interface engineering based on Y2O3 has a potential to open up a new avenue to high-performance AlGaN/GaN MOS-HEMTs.
Rational Design of ZnO:H/ZnO Bilayer Structure for High Performance Thin-Film Transistors
(2016-03-30)
Abliz, Ablat
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Huang, Chun-Wei
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Wang, Jingli
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Xu, Lei
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Liao, Lei
The intriguing properties of zinc oxide-based semiconductors are being extensively studied as they are attractive alternatives to current silicon-based semiconductors for applications in transparent and flexible electronics. Although they have promising properties, significant improvements on performance and electrical reliability of ZnO-based thin film transistors (TFTs) should be achieved before they can be applied widely in practical applications. This work demonstrates a rational and elegant design of TFT, composed of poly crystalline ZnO:H/ZnO bilayer structure without using other metal elements for doping. The field-effect mobility and gate bias stability of the bilayer structured devices have been improved. In this device structure, the hydrogenated ultrathin ZnO:H active layer (similar to 3 nm) could provide suitable carrier concentration and decrease the interface trap density, while thick pure-ZnO layer could control channel conductance. Based on this novel structure, a high field-effect mobility of 42.6 cm(2) V-1 s(-1), a high on/off current ratio of 108 and a small subthreshold swing of 0.13 V dec(-1) have been achieved. Additionally, the bias stress stability of the bilayer structured devices is enhanced compared to the simple single channel layer ZnO device. These results suggest that the bilayer ZnO:H/ZnO TFTs have a great potential for low-cost thin-film electronics.