Browsing by Author "Wang, Kuan-Ti"

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A Novel p-n-Diode Structure of SONOS-Type TFT NVM With Embedded Silicon Nanocrystals
(2010-11-01)
Chiang, Tsung-Yu
;
Ma, William Cheng-Yu
;
Wu, Yi-Hong
;
Wang, Kuan-Ti
;
Chao, Tien-Sheng
In this letter, for the first time, a novel p-n-diode (PND) structure of SONOS-type thin-film transistor (TFT) nonvolatile memory (NVM) with embedded silicon nanocrystals (Si-NCs) in the silicon nitride layer using an in situ method is successfully demonstrated. This novel structure has many advantages, including high density and suitability for 3-D circuit integration. Hot-electron injection and hot-hole injection are used as the program and erase methods, respectively. The sensing current of the three-terminal PND-TFT NVM is 10(-7) A by the band-to-band tunneling current. A much larger memory window (> 12 V) and good data retention time (> 10(8) s for 12% charge loss) are exhibited. The device appears to have great potential for system-on-panel applications.
A Novel p-n-Diode Structure of SONOS-Type TFT NVM With Embedded Silicon Nanocrystals
(2010-11-01)
Chiang, Tsung-Yu
;
Ma, William Cheng-Yu
;
Wu, Yi-Hong
;
Wang, Kuan-Ti
;
Chao, Tien-Sheng
In this letter, for the first time, a novel p-n-diode (PND) structure of SONOS-type thin-film transistor (TFT) nonvolatile memory (NVM) with embedded silicon nanocrystals (Si-NCs) in the silicon nitride layer using an in situ method is successfully demonstrated. This novel structure has many advantages, including high density and suitability for 3-D circuit integration. Hot-electron injection and hot-hole injection are used as the program and erase methods, respectively. The sensing current of the three-terminal PND-TFT NVM is 10(-7) A by the band-to-band tunneling current. A much larger memory window (> 12 V) and good data retention time (> 10(8) s for 12% charge loss) are exhibited. The device appears to have great potential for system-on-panel applications.
Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon Nanocrystals
(2010-08-01)
Chiang, Tsung-Yu
;
Wu, Yi-Hong
;
Ma, William Cheng-Yu
;
Kuo, Po-Yi
;
Wang, Kuan-Ti
In this paper, silicon-oxide-nitride-oxide-semiconductor (SONOS) devices with embedded silicon nanocrystals (Si-NCs) in silicon nitride using in situ method with multilevel and 2-b/cell operation have been successfully demonstrated. The proposed in situ Si-NC deposition method exhibits the advantages of low cost, simplicity, and compatibility with modern IC processes. SONOS memories with embedded Si-NCs exhibit a significantly improved performance with a large memory window (> 5.5 V), low operating voltage (P/E voltage: V(g) = 6 V, V(d) = 7 V and V(g) = -7 V, V(d) = 10 V, respectively), greater tolerable gate and drain disturbance (V(t) shift < 0.2 V), negligible second-bit effect, high P/E speed (after programming time = 10 mu s with a 2-V shift of V(t) under V(g) = V(d) = 6 V operation), good retention time (> 10(8) s for 13% charge loss), and excellent endurance performance (after 10(4) P/E cycles with a memory window of 3 V).
High-Reliability Dynamic-Threshold Source-Side Injection for 2-Bit/Cell With MLC Operation of Wrapped Select-Gate SONOS in NOR-Type Flash Memory
(2010-09-01)
Wang, Kuan-Ti
;
Chao, Tien-Sheng
;
Wu, Woei-Cherng
;
Yang, Wen-Luh
;
Lee, Chien-Hsing
For the first time, a high-performance (tau(PGM) = 200 ns/tau(ERS) = 5 ms) cell with superior reliability characteristics is demonstrated in a NOR-type architecture, using dynamic-threshold source-side injection (DTSSI) in a wrapped select-gate silicon-oxide-nitride-oxide-silicon memory device, with multilevel and 2-bit/cell operation. Using DTSSI enables easy extraction of the multilevel states with a tight V(TH) distribution, a nearly negligible second-bit effect, superior endurance characteristics, and good data retention.
High-Speed Multilevel Wrapped-Select-Gate SONOS Memory Using a Novel Dynamic Threshold Source-Side-Injection (DTSSI) Programming Method
(2009-06-01)
Wang, Kuan-Ti
;
Chao, Tien-Sheng
;
Wu, Woei-Cherng
;
Chiang, Tsung-Yu
;
Wu, Yi-Hong
A. high programming speed with a low-power-consumption wrapped-select-gate poly-Si-oxide-nitride-oxide-silicon memory is successfully demonstrated using the novel dynamic threshold source-side-injection programming technique. The select gate embedded in such particular memory structure acts like a dynamic MOSFET resulting in programming current (I(PGM)) that can be enhanced in this DT mode, easily attaining a high programming speed of about 100 ns. It still doubles the memory density by achieving the 2-bit/cell operation with MLC under DT mode.
MILC-TFT With High-kappa Dielectrics for One-Time-Programmable Memory Application
(2009-09-01)
Chiang, Tsung-Yu
;
Ma, Ming-Wen
;
Wu, Yi-Hong
;
Kuo, Po-Yi
;
Wang, Kuan-Ti
In this letter, for the first time, one-time-programmable (OTP) memory fabricated on the low-temperature poly-Si p-cbannel thin-film transistor (TFT) with metal-induced lateral-crystallization channel layer and high-kappa dielectrics is demonstrated. The state of this OTP memory can be identified by the scheme of gate-induced drain leakage current measurement. The OTP-TFT memory has good electrical characteristics in terms of low threshold voltage V(th) similar to -0.78 V, excellent subthreshold swing similar to 105 mV/dec, low operation voltage, faster programming speeds, and excellent reliability characteristics.
Novel 2-Bit/Cell Wrapped-Select-Gate SONOS TFT Memory Using Source-Side Injection for NOR-Type Flash Array
(2012-06-01)
Wang, Kuan-Ti
;
Hsueh, Fang-Chang
;
Lu, Yu-Lun
;
Chiang, Tsung-Yu
;
Wu, Yi-Hong
This letter is the first to successfully demonstrate the 2-bit/cell wrapped-selected-gate (WSG) SONOS thin-film transistor (TFT) memory using source-side injection (SSI). Because of the higher programming efficiency of SSI, a memory window of approximately 3 V can be easily achieved in 10 mu s and 30 ms for the program and erase modes, respectively. In addition, we performed an excellent 2-bit/cell distinguish margin for 3-V memory window in WSG-SONOS TFT memory. The optimal reliability of the endurance and data retention tests can be executed by adjusting the applied voltage appropriately.
Physical Mechanism of High-Programming-Efficiency Dynamic-Threshold Source-Side Injection in Wrapped-Select-Gate SONOS for NOR-Type Flash Memory
(2009-11-01)
Wang, Kuan-Ti
;
Chao, Tien-Sheng
;
Chiang, Tsung-Yu
;
Wu, Woei-Cherng
;
Kuo, Po-Yi
For the first time, a programming mechanism for conventional source-side injection (SSI) (normal mode), substrate-bias enhanced SSI (body mode), and dynamic-threshold SSI (DTSSI) (DT mode) of a wrapped-select-gate SONOS memory is developed with 2-D Poisson equation and hot-electron simulation and programming characteristic measurement for NOR Flash memory. Compared with traditional SSI, DTSSI mechanisms are determined in terms of lateral acceleration electric field and programming current (I(PGM)) in the neutral gap region, resulting in high programming efficiency. Furthermore, the lateral electric field intersects the vertical electric field, indicating that the main charge injection point is from the end edge of the gap region close to the word gate.
Symmetric Vertical-Channel Nickel-Salicided Poly-Si Thin-Film Transistors With Self-Aligned Oxide Overetching Structures
(2011-07-01)
Wu, Yi-Hong
;
Kuo, Po-Yi
;
Lu, Yi-Hsien
;
Chen, Yi-Hsuan
;
Chiang, Tsung-Yu
This paper reports the impacts of NH(3) plasma treatment time, oxide overetching depth, and gate oxide thickness on symmetric vertical-channel Ni-salicided poly-Si thin-film transistors (VSA-TFTs) for the first time. OFF-state currents may be improved by increasing the oxide overetching depth. The ON/OFF current ratio may be also improved by increasing the oxide overetching depth. The NH(3) plasma optimum treatment time of VSA-TFTs is significantly shorter than that of conventional top-gate horizontal-channel TFTs. The performance of VSA-TFTs is degraded by NH(3) plasma treatment for too long a time. VSA-TFTs with 15-nm gate oxide thickness display better subthreshold swing (< 150 mV/dec) than VSA-TFTs with 30-nm gate oxide thickness. OFF-state currents can be improved by increasing L(mask), even when the oxide overetching depth and the gate oxide thickness are changed.
The polarity dependence of ONO thickness for wrapped-select-gate (WSG) SONOS memory
(2008)
Wang, Kuan-Ti
;
Chao, Tien-Sheng
;
Wu, Woei-Cherng
;
Lai, Chao-Sung
;
電子物理學系
2-bits/cell operation characteristics of WSG-SONOS memory has been fully studied in different ONO thickness. The 2-bits/cell characteristics of WSG-SONOS memory will be determined by tunneling oxide and total ONO thicknesses. Besides, thicker top oxide thickness will contribute to better gate disturbance performance while maintaining the same drain disturbance. We also found that the excellent endurance can be performed for the device with thinner tunneling oxide thickness. Optimized ONO thickness for WSG-SONOS memory will be demonstrated in this paper.
The Zero-Temperature-Coefficient Point Modeling of DTMOS in CMOS Integration
(2010-10-01)
Wang, Kuan-Ti
;
Lin, Wan-Chyi
;
Chao, Tien-Sheng
;
電子物理學系
;
Department of Electrophysics
For the first time, analytical expressions of zero-temperature-coefficient (ZTC) point modeling of DTMOS transistor are successfully presented in detail. New analytical formulations for the linear and saturation regions of DTMOS transistor operation that make certain the drive current to be temperature independent for the ideal gate voltage are developed. The maximum errors of 0.87% and 2.35% in the linear and saturation regions, respectively, confirm a good agreement between our DTMOS ZTC point model and the experimental data. Compared to conventional MOSFET, the lower V(g) (ZTC) with higher overdrive current of DTMOS improves the integrated circuit speed and efficiency for the low-power-consumption concept in green CMOS technology.