Browsing by Author "Wang, Min-Jer"

Now showing 1 - 4 of 4

A 0.42V Vccmin ASIC-Compatible Pulse-Latch Solution as a Replacement for a Traditional Master-Slave Flip-Flop in a Digital SOC
(2014)
Dhong, Sang
;
Guo, Richard
;
Kuo, Ming-Zhang
;
Yang, Ping-Lin
;
Lin, Cheng-Chung
We present a pulse latch with a measured Vccmin at the circuit of 0.42 V and pulse width of approximately 3 FO4-inverter delays. A wider operating window and reduced dependence on the input rise-time and PVT variations were obtained using a new pulse generator. A pulse in the new generator starts when its input crosses the switching level of its input gate, unlike in the classic text-book-style pulse-generator. An 8 to 10% improvement in power, performance, and area (PPA) of a typical digital SOC is observed when a group of pulse latches is driven by a distributed clock regenerator (OCR). The OCR has the new pulse generator at its input stage and provides pulse clocks to the pulse latches. Experimental results in a 28-nm HKMG process closely match SPICE simulations.
A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application
(2014-04-01)
Lin, Mu-Shan
;
Tsai, Chien-Chun
;
Chang, Chih-Hsien
;
Huang, Wen-Hung
;
Hsu, Ying-Yu
A 1 Tbit/ s bandwidth PHY is demonstrated through CoWoS(TM) platform. Two chips: SOC and embedded DRAM ( eDRAM), have been fabricated in TSMC 40 nm CMOS technology and stacked on a silicon interposer chip. 1024 DQ buses operating at 1.1 Gbit/ s with VDDQ = 0.3 V are proven between SOC chip and eDRAM chip in experimental results with 1 mm signal trace length on the silicon interposer. A novel timing compensation mechanism is presented to achieve a low- power and small area eDRAM PHY that excludes PLL/ DLL but retains good timing margin. Another data sampling alignment training approach is employed to enhance timing robustness. A compact low- swing IO also achieves power efficiency of 0.105 mW/ Gbps.
A 16kB Tile-able SRAM Macro Prototype for an Operating Window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS
(2014)
Kuo, Ming-Zhang
;
Hsieh, Henry
;
Dhong, Sang
;
Yang, Ping-Lin
;
Lin, Cheng-Chung
This paper describes a tile-able 16-kByte 6-T SRAM macro in a High-K Metal-Gate (HKMG) 28-nm bulk technology with an operating window from 4.8 GHz at 1.12 V VDD down to 10 MHz at 0.5V, meeting almost all of the Dynamic Voltage Frequency Scaling (DVFS) requirements of Level-1 (L1) caches of a digital microprocessor SOC. It uses an unmodified technology-supported 0.156um(2) high-current (HC) SRAM cell. Innovative and carefully optimized circuit solutions provide the wide operating range measured in hardware. We also discuss two circuit improvements, a cross-coupled PMOS-pair for each bitline-pair with mux readout and an independently-controlled precharge-and-write driver (ICPW), which gives a wider DVFS operating window with reduced sensitivities to Process-Voltage-Temperature (PVT) variations. Improved SRAM macros with new circuits have been designed and laid out and their performance and area verified in simulation.
Custom 6-R, 2-or 4-W Multi-Port Register Files in an ASIC SOC with a DVFS Window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS Technology
(2015)
Hsieh, Henry
;
Dhong, Sang H.
;
Lin, Cheng-Chung
;
Kuo, Ming-Zhang
;
Tseng, Kuo-Feng
We describe custom 6R, 2/4W general-purpose register files (GRF) in an ASIC-based SOC implemented in a N28 CMOS technology, which has roughly a 2 similar to 3 X smaller area, 2 X faster speed, and 5 X lower power than a logic synthesized version. Synthesized and custom GRFs also have a different read behavior from static and dynamic circuitry used, respectively. This is addressed by modifying a bypass control block. Hardware showed a DVFS window of 0.5 V @ccuit, 130 MHz to 0.96 V, 3.2 GHz.