Browsing by Author "Wang, Shih-Ming"

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92% High Efficiency and Low Current Mismatch Interleaving Power Factor Correction Controller With Variable Sampling Slope and Automatic Loading Detection Techniques
(2013-11-01)
Su, Yi-Ping
;
Chen, Chun-Yen
;
Ni, Chia-Lung
;
Kang, Yu-Chai
;
Chen, Yi-Ting
This paper proposes the dual nondeadtime variable sampling slope technique to carry out precise phase sensing and suppress phase error in interleaving power factor correction (PFC) controller over a whole ac switching cycle for low current mismatch. Furthermore, the proposed automatic loading detection (ALD) technique can keep efficiency higher than 92% over a wide load range due to accurately controlling the ON/OFF of dual phases. The test circuit fabricated in the TSMC 0.5-mu m 800-V UHV process shows that the highly integrated interleaving PFC can deliver a high power of 180 W and a high efficiency of 95% at an output power of 180 W.
A Dual-Level Dual-Phase Pulse-Width Modulation Class-D Amplifier with 0.001% THD, 112 dB SNR
(2014-01-01)
Yang, Shang-Hsien
;
Yang, Yuan-Han
;
Chen, Ke-Horng
;
Hung, Chung-Chih
;
Wey, Chin-Long
this paper presents a dual-level dual-phase pulse-width modulation (DLDP PWM) Class-D audio amplifier circuit which enhance amplifier linearity and reduce distortion. The proposed DLDP PWM Class-D audio amplifier includes two sets of non-overlapping triangular waves, each at its respectful offset levels. Each set of triangular waves is composed of two 180 degrees out-of-phase triangular waves. The differential power stage consists of 8 power transistors, with voltage swings up to +/- 6V. Simulated results shows that the proposed DLDP PWM Class-D audio amplifier features an SNR up to 105 dB, and the THD is suppressed below 0.001 %, with the 3rd harmonic below -102 dBV.
A Low THD Clock-Free Class-D Audio Amplifier with an Increased Damping Resistor and Cross Offset Cancellation Technique
(2014-01-01)
Chou, Ying-Wei
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Chien, Meng-Wei
;
Chen, Shin-Chieh
;
Chen, Ke-Horng
;
Lin, Ying-Hsi
an increased damping resistor (IDR) replaces high-order loop filter to simply reduce the total harmonic distortion (THD) of Class-D audio amplifier. Besides, cross offset cancellation (COC) technique minimizes the system offset voltage to avoid dc current flows to the speaker in the bridge tied load (BTL) structure. Furthermore, variable switching frequency characteristic in self-oscillating modulation spreads the electro-magnetic interference (EMI) impact out on the output frequency spectrum. Experimental results demonstrate that the proposed Class-D amplifier can deliver 0.55W to the 8 Omega load with a 3.3V supply voltage with 150-nm CMOS process. The power efficiency is over 90% and the output THD is smaller than 0.01% (80dB).
A Pseudo Fixed Switching Frequency 2kHz/A in Optimum On-Time Control Buck Converter with Predicting Correction Technique for EMI Solution
(2014-01-01)
Chen, Wei-Chung
;
Lin, Kuei-Liang
;
Chen, Ke-Horng
;
Lin, Ying-Hsi
;
Tsai, Tsung-Yen
This paper repots an optimum on-time (OOC) control with predicting correction technique (PCT) for ripple-based buck converter. The switching frequency (F-SW) variation is analyzed with completely considering the parasitic resistances of the components and devices. The proposed converter achieved nearly constant switching frequency over a wide load range without extra clock controlled circuits and current sensing circuits. The parameters of the parasitic resistances almost cause no influence and no restriction on F-SW performance. Actually, only the input voltage is necessary to predict the optimum on-time, and this work benefits the decease on total pin numbers. The simulation results demonstrate 0.375% Delta F-SW/F-SW and 2kHz/A Delta F-SW/Delta I-LOAD over 1.5A load current change. Consequently, pseudo constant F-SW with known noise spectrum strongly benefits the solution of electromagnetic interference (EMI) issue for system-on-chip (SoC).
A software configurable coupler with programmable coupling coefficient
(2007)
Wang, Shih-Ming
;
Chang, Chi-Yang
;
Lin, Jenshan
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電信工程研究所
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Institute of Communications Engineering
A novel microstrip parallel coupler with tunable coupling coefficient is proposed. Two varactors are placed on microstrip parallel-coupled lines to tune the coupling coefficient. With proper combinations of the capacitances of two varactors, the coupling coefficient can be tuned from 10 dB to 6 dB with good return loss and directivity. By using the Labview program and data acquisition component, at software configurable coupler is implemented. This software configurable coupler will be useful in microwave instrumentation.
Automatic Power Monitor (APM) in Switching Charger with Smooth Transition Loop Selector (STLS) for High-energy Throughput System
(2012)
Tsai, Tsu-Wei
;
Peng, Ruei-Hong
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Su, Yi-Ping
;
Chen, Ya-Ping
;
Chen, Ke-Horng
This paper proposed a switch-based charger system instead of LDO-based charger for Li-Ion batteries. The automatic power monitor (APM) controls three main power delivery paths to generate five different charging cases. Moreover, with the proposed smooth transition loop selector (STLS), the charging process can transfer smoothly and never oscillate between two consecutive stages. Furthermore, the STLS can bear different batteries with wide built-in resistance variation by adjusting charging factors. The stability analysis proves that the stability of APM loop is guaranteed by only one Type-III compensator. The simulation results ensure the performance of the system controlled by APM even if the power source is unable to provide sufficient power.
Microstrip band-pass filters with wide stopband and sharper cutoff response
(2005)
Hsieh, Ming-Yu
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Wang, Shih-Ming
;
Liao, Ching-Ku
;
Chiang, Chin-Hsien
;
Chang, Chi-Yang
In this paper, a microstrip band-pass filter (BPF) with the sharper cutoff rate and suppression of the 2(nd), 3(rd), and 4(th) harmonics is developed. The half wavelength transmission resonator with a pair of tap-connected open-ended stubs is adopted for constructing filter with band-edge attenuation poles. Using resistive attenuator and adequate coupling, structures can suppress the unwanted harmonics. The resonance characteristic of resonator with embedded attenuator is analyzed with the aid of unloaded quality factor. By means of controlling the coupling structures, the embedded resistive attenuator, and the resonator with tap-connected stubs, the proposed bandpass filters can easily achieve a wide stopband and a sharp skirt property. Band-pass filter of center frequency at 1.96GHz was implemented to confirm our ideas.
Reduction of Equivalent Series Inductor Effect in Delay-Ripple Reshaped Constant On-Time Control for Buck Converter with Multi-layer Ceramic Capacitors
(2012)
Chen, Wei-Chung
;
Kang, Yu-Chi
;
Lin, Chia-Ching
;
Chen, Ke-Horng
;
Wang, Shih-Ming
The time constant, which is the product of the output capacitor and its equivalent series resistance (ESR), limits the stability of conventional constant on-time control buck converter. To meet the expected requirements, SP-CAP is mostly used as output capacitor although it deteriorates the performance of converter. On the other hand, the multi-layer ceramic capacitors (MLCC) features low cost and small equivalent series resistance (ESR) and is widely used in commercial power management ICs. However, the stability often suffers from the sub-harmonic problem due to small time constant. This paper proposes a differential-zero compensator with the noise margin enhancement (DZC-NME) technique in constant on-time control buck DC-DC converter with ceramic output capacitor. The proposed DZC-NME technique not only eliminates the limit of large time constant but also tolerates the existence of equivalent series inductor (ESL) effect. Simulation result demonstrates the function and shows smaller output ripple of 10mV and high efficiency of 91 % with ESR which smaller than 1m Omega.
Variable Sampling Slope (VSS) and No-Deadtime Ramp Generator (NDRG) Techniques for Closed-Loop Interleaving Power Factor Correction (PFC) Design with Suppression of Current Mismatch
(2012)
Chen, Chun-Yen
;
Peng, Ruei Hong
;
Tsai, Jen-Chieh
;
Kang, Yu-Chi
;
Ni, Chia-Lung
the proposed interleaving power factor correction (PFC) can effectively reduce the size of the AC-DC converter for portable electronics. Fully integrated variable sampling slope (VSS) technique can provide precise phase regulation under variable line voltage. Besides, the no-deadtime ramp generator (NDRG) records the previous status to modify the sequent on-time value to achieve current sharing for suppressing the total harmonic distortion (THD) and restraining the input current ripple, EMI filter, and the size of input inductor. Therefore, more power can be provided by the proposed interleaving PFC than that of single-phase PFC. Simultaneously, the drawback of the peak current twice than the average current in the Boundary control mode (BCM) can be greatly reduced. The test circuit fabricated in the TSMC 0.5 mu m 800V UHV process shows the highly integrated interleaving PFC can deliver high power of 180W with improved phase regulation precision.