Browsing by Author "Wang, Wen-Tai"

Now showing 1 - 4 of 4

A 28nm 36kb High Speed 6T SRAM with Source Follower PMOS Read and Bit-Line Under-Drive
(2015)
Hong, Chi-Hao
;
Chiu, Yi-Wei
;
Zhao, Jun-Kai
;
Jou, Shyh-Jye
;
Wang, Wen-Tai
In this paper, we present source follower PMOS Read and bit-line under-drive techniques to improve the operation speed as compared to present commercial SRAM compilers. A source follower PMOS is utilized to connect local bit-lines (LBL) to global bit-lines (GBL) instead of using a NAND gate. To further improve the discharging time from LBL to GBL, we propose a bit-line under-drive circuit to reduce the voltage level of LBL. The simulated access time of the proposed macro is 445 ps at slow N slow P (SS) corner, -40 degrees C, 0.81 V. As compared to the SRAM macro which is generated by commercial SRAM compilers with the fastest combination, the access time of the proposed SRAM macro is 12% faster than that of commercial SRAM compilers. A 36kb high speed 6T SRAM macros with source follower PMOS Read and bit-line under-drive techniques is fabricated in 28nm HKMG CMOS process. The measurement results of the chip in SS corner show the proposed SRAM macro passes all MBIST patterns at 500 MHz at 0.81 V, room temperature.
ESD Protection Design with Low-Leakage Consideration for Silicon Chips of IoT Applications
(2017-01-01)
Ker, Ming-Don
;
Lin, Chun-Yu
;
Wu, Yi-Han
;
Wang, Wen-Tai
;
電子工程學系及電子研究所
On-chip electrostatic discharge (ESD) protection design with low-leakage consideration for the silicon chips of IoT applications is presented. The proposed ESD protection design uses the fast turn-on silicon-controlled rectifier (SCR) device to implement the power-rail ESD clamp circuit. Experimental results verified in TSMC 28nm CMOS process have shown that the proposed design has advantages of low leakage current (2 similar to 3nA), low trigger voltage (similar to 2V), high ESD robustness (>8kV), and free to latchup issue.
Study on the ESD-Induced Gate-Oxide Breakdown and the Protection Solution in 28nm High-K Metal-Gate CMOS Technology
(2015)
Lin, Chun-Yu
;
Ker, Ming-Dou
;
Chang, Pin-Hsin
;
Wang, Wen-Tai
;
電子工程學系及電子研究所
To protect the IC chips against the electrostatic discharge (ESD) damages in 28nm high-k metal-gate (HKMG) CMOS technology, the ESD protection consideration was studied in this work. The ESD design window was found to be within 1V and 5.1V in 28nm HKMG CMOS technology. An ESD protection device of PMOS with embedded silicon-controlled rectifier (SCR) was investigated to be suitable for ESD protection in such narrow ESD design window.
Vertical SCR Structure for On-Chip ESD Protection in Nanoscale CMOS Technology
(2015)
Lin, Chun-Yu
;
Chang, Pin-Hsin
;
Chang, Rong-Kun
;
Ker, Ming-Dou
;
Wang, Wen-Tai
A vertical silicon-controlled rectifier (SCR) structure utilizing ESD implantation layer was proposed and implemented in nanoscale CMOS technology. Compared with the traditional SCR structure, the proposed structure has lower trigger voltage and high enough ESD protection capability. Therefore, the proposed structure was suitable for ESD protection in nanoscale CMOS process.