Browsing by Author "Wong, Oi-Ying"

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A Fully-Integrated Charge Pump for Self-Powered Implantable Retinal Prostheses
(2016)
Wong, Oi-Ying
;
Chen, Po-Hung
;
Wu, Chung-Yu
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電子工程學系及電子研究所
;
生醫電子轉譯研究中心
This paper presents a compact fully-integrated charge pump based voltage doubler for self-powered implantable retinal prostheses. The target input voltage is 0.55 V to meet the output voltage of on-chip photovoltaic cells, and the target output is around 1 V to provide sufficient current for neuron stimulation. Several techniques are adopted in the proposed design, including gate-boosting circuits to enhance current driving capability, a time-interleaving technique to reduce the size of the output capacitor, and a non-overlapping clock generator to suppress the shoot-through current. The proposed charge pump was implemented in 0.18 mu m CMOS process with core chip area of 700 mu m x 280 mu m. The measurement results demonstrate that the proposed charge pump is capable of providing around 1 V output from an input voltage of 0.55 V with 500 mu A loading current. The peak power efficiency is 73.4 % and the total area is 700 mu m x 280 mu m.
Energy Harvesting Techniques: Energy Sources, Power Management and Conversion
(2015)
Fan, Philex Ming-Yan
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Wong, Oi-Ying
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Chung, Ming-Jie
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Su, Tze-Yun
;
Zhang, Xin
Energy harvesting techniques have been developed more than a decade and received much attention in realizing long-term energy autonomous microsystems. Many converter topologies and circuit techniques have been reported to effectively convert the harvested energy to usable outputs. In this paper, major green energy sources as well as the equivalent circuits are reviewed. In addition, maximum power point tracking (MPPT) technique and power conversion topologies are also included.
First Fully Functionalized Monolithic 3D(+) IoT Chip with 0.5 V Light-electricity Power Management, 6.8 GHz Wireless-communication VCO, and 4-layer Vertical ReRAM
(2016-01-01)
Hsueh, Fu-Kuo
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Shen, Chang-Hong
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Shieh, Jia-Min
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Li, Kai-Shin
;
Chen, Hsiu-Chih
For the first time, we report low-cost heterogeneously integrated sub-40nm epi-like Si monolithic internet of thins (IoT) 3D(+)-IC with wireless communication, light-electricity power management and vertical ReRAM (VRRAM) modules. High current driving multi-channel 3D(+) UTB-MOSFETs (600 mu A/282 mu A@V-G = +/- 1V for 10-channel P/N FETs) was fabricated by low thermal budget super-CMP-planarized visible laser-crystallized epi-like Si channel and CO2 far-infrared laser annealing (CO2-FIR-LA) activation technologies that support a 6.8GHz high frequency VCO circuits, 0.5V low-voltage power management circuit and drives 20nm 4-layer VRRAM (Set/Reset <1.2V/1.8V, 3-bits/cell). This unique TSV-free monolithic 3D(+)IC process provides the superiority in 3D hetero-integration; we successfully integrate these circuits in a low cost, small footprint, fully functionalized 3D(+) IoT chip.
Fully Integrated Voltage Doubler With Dual-Mode Three-Dimensional Load Regulation for On-Chip Photovoltaic-Powered Applications
(2019-02-01)
Wong, Oi-Ying
;
Chen, Po-Hung
;
電子工程學系及電子研究所
;
生醫電子轉譯研究中心
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a compact and fully integrated switched-capacitor voltage doubler for voltage boosting in photovoltaic-powered implantable devices. Gate-voltage boosting, nonoverlapping, and interleaving techniques are adopted to enhance the driving capability of the voltage doubler at low supply voltage with high efficiency. A dual-mode three-dimensional (3-D) digital control circuit is proposed to regulate the output voltage under the load current variation. The 3-D control on the number of active converter cells, operation frequency, and ON-resistance enable fine output voltage regulation over a wide load current range without extensive device segmentation, thereby reducing the routing complexity and the associated parasitic losses. Other advantages are that the switching loss can be proportionally scaled with the load current for high power efficiency and the periodic charge transfer to the output can keep small for small voltage ripple. Pulse-skipping modulation is employed to allow the converter to operate under ultra-light load. The proposed voltage doubler is designed and implemented using 0.18 mu m-CMOS process. The measurement results demonstrate that the proposed converter can generate a voltage of 0.9 V from an input of 0.6 V, with a power efficiency of more than 60% within the output current range of 30440 mu A. The peak efficiency is 73% and the active area is 0.33 mm(2). These measurement results suggest that the proposed voltage doubler is suitable for voltage boosting at low voltage under the limited availability of power and area.
Improved Charge Pump Design and Ex Vivo Experimental Validation of CMOS 256-Pixel Photovoltaic-Powered Subretinal Prosthetic Chip
(2020-05-01)
Kuo, Po-Han
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Wong, Oi-Ying
;
Tzeng, Chi-Kuan
;
Wu, Pu-Wei
;
Chiao, Chuan-Chin
An improved design of CMOS 256-pixel photovoltaic-powered implantable chip for subretinal prostheses is presented. In the proposed subretinal chip, a high-efficiency fully-integrated 4x charge pump is designed and integrated with on-chip photovoltaic (PV) cells and a 256-pixel array with active pixel sensors (APS) for image light sensing, biphasic constant current stimulators, and electrodes. Thus the PV voltage generated by infrared (IR) light can be boosted to above 1V so that the charge injection is increased. The proposed chip adopts the 32-phase divisional power supply scheme (DPSS) to reduce the required supply current and thus the required area of the PV cells. The proposed chip is designed and fabricated in 180-nm CMOS image sensor (CIS) technology and post-processed with biocompatible IrOx electrodes and silicone packaging. From the electrical measurement results, the measured stimulation frequency is 28.3 Hz under the equivalent electrode impedance load. The measured maximum output stimulation current is 7.1 mu A and the amount of injected charges per pixel is 7.36 nC under image light intensity of 3200 lux and IR light intensity of 100 mW/cm(2). The function of the proposed chip has been further validated successfully with the ex vivo experimental results by recording the electrophysiological responses of retinal ganglion cells (RGCs) of retinas from retinal degeneration (rd1) mice with a multi-electrode array (MEA). The measured average threshold injected charge is about 3.97 nC which is consistent with that obtained from the patch clamp recording on retinas from wild type (C57BL/6) mice with a single electrode pair.