Browsing by Author "Wu"

Now showing 1 - 12 of 12

Algorithm for a memory-based Viterbi decoder
(2007-08-28)
Lee
;
Chen-Yi
;
Lin
;
Chien-Ching
;
Wu
A method of convolutional decoding with a memory-based Viterbi decoder employs the property of a trace-back path; that is, the similarity between two consecutive trace-back paths becomes higher as the data error rate goes down. Therefore, the method of the invention saves the previous trace-back path into a register, and as soon as the current trace-back path is found to be the same as the previous one, the demanded path is obtained. After that, the memory read operations will stop, thereby reducing the power consumption caused by memory read operations. Prior to path trace-back, the path prediction can be executed by utilizing the property that the minimum path metric and the path are consecutive. The invention reduces the number of memory access operations and power consumption by employing the mechanisms of path matching and path prediction.
Architecture of an embedded internet robot system controlled by brain waves
(2007-08-21)
Wu
;
Li-Wei
;
Liao
;
Hsien-Cheng
The present invention discloses an architecture of an embedded internet robot system controlled by brain waves, wherein the brain-computer interface and the internet robot system cooperate with the alertness level detection technology and the instruction translation technology, and thereby, the user can control a distal-end robot purely via consciousness activities and can interact with the environment as if there were an entity representing the user's consciousness appearing in the distal end. The seriously disabled person can regain his expressive ability via the present invention. Further, the present invention can also be applied to a multi-player interactive game system.
Background calibration system for calibrating non-linear distortion of amplifier and method thereof
(2010-10-26)
Fan
;
Jen-Lin
;
Wu
;
Jieh-Tsorng
The present invention discloses a background calibration system and method for calibrating the non-linear distortion of the amplifier. The calibration method in the present invention includes: generating random sequences and inputting the random sequences in different amount and different sets into an amplifier; amplifying the random sequences and detecting linear and non-linear coefficients; quantizing the output linear signal from the amplifier, and generating a digital output signal; multiplying the digital output signal to generate a high-order signal; generating an estimated non-linear error for the amplifier by multiplying the high-order signal with the estimated non-linear coefficient; adding the non-linear signal with the digital output signal to generate a linear output signal; calculating the random value from the parameter extractor to determine the occurrence of non-linear distortion in the circuit, and further adjusting the non-linear coefficient to calibrating the amplifier.
Background comparator offset calibration technique for flash analog-to-digital converters
(2006-06-20)
Huang
;
Chun-Cheng
;
Wu
;
Jieh-Tsorng
A background-calibrated comparator and a background-calibrated flash analog-to-digital converter are disclosed for using in mixed-signal integrated circuit design in particular on the high-speed analog-to-digital converter circuit. Without affecting the operation of the comparator, the disclosure is directed at reducing the unpredictable input offset voltage originated from the variation of process parameters and environmental factors. The background-calibrated comparator includes a random chopping comparator, a calibration processor, and a random sequence generator. The background-calibrated flash analog-to-digital converter (ADC) includes a background-calibrated comparator array together with a reference voltage generator, a thermometer code edge detector, and a set of digital encoders.
Clock switching circuit
(2007-08-21)
Wu
;
Jian-Hua
;
Hwang
;
Wei
The present invention discloses a clock switching circuit, which comprises: a clock generator, receiving two different clock signals; a logic gate, coupled to an enable-signal generator and an output-clock generator, wherein during clock switching, the logic gate turns off output clock according to the signal edges of those two clock signals to avoid the problems of clock glitch and timing insufficiency, and the logic gate will not restore clock output until an appropriate timing occurs.
Method for transferring epitaxy layer
(2004-02-03)
Wu
;
YewChung Sermon
;
Lin
;
PeiYan
A method for transferring an epitaxy layer is provided. The method includes steps of (a) providing a first substrate, (b) forming a first epitaxy layer on the first substrate, (c) forming a masking layer having at least a pattern on the first epitaxy layer, (d) forming a second epitaxy layer on the masking layer, (e) bonding a second substrate to the second epitaxy layer, and (f) removing the masking layer and separating the second epitaxy layer from the first epitaxy layer, thereby the second epitaxy layer being transferred to the second substrate.
Method of alignments of liquid crystal employing magnetic thin films
(2010-06-01)
Chao
;
Ru-Pin
;
Wu
;
Hsin-Ying
Alignments of liquid crystal are obtained. A transparent magnetic thin film provides a homeotropic alignment of liquid crystal molecules. Or, a homeotropic or homogeneous alignment having an adjustable pretilt angle is further obtained through rubbing the transparent magnetic thin film. The present invention has a simple procedure with a low cost. The present invention is used in equipment with a plasma source while providing high transmittance, hardness and insulation. And the transparent magnetic thin film has potential uses in the applications of non-contact multi-domain alignment without extra procedure for alignment treatment.
Method of combining multilevel memory cells for an error correction scheme
(2007-07-10)
Wu
;
Jieh-Tsorng
;
Wang
;
Ta-Hui
;
Chang
A memory combines plural memory cells for storing data wherein the differential stages voltage levels of memory cells are not limited in square value of 2 and can be improved linearly. The feature of the present invention can also increase memory capacity without increasing memory area. Furthermore it can remain voltage levels which cannot express 0 and 1 combination for error erasure messages when data is read. For efficient usage of memory, the increased memory capacity is not only for storing data but also for storing error correction scheme to assure the veracity of the storing data and improve producing yield and reliability for multilevel memory systems.
Method of symbol detection for MIMO dual-signaling uplink CDMA systems
(2010-02-16)
Ho
;
Chung-Lien
;
Wu
;
Jwo-Yuh
;
Lee
The invention provides a block-wise successive interference cancellation (SIC) detection algorithm for a general multi-input multi-output (MIMO) CDMA system over the frequency-selective channels, in which each user's data stream can be simultaneously applied with orthogonal space-time block encoding for transmit diversity or spatially multiplexing for high spectral efficiency according to the channel conditions. For such the considered dual-signaling system, the receiver could suffer from the large dimension data processing. A two-stage approach for block-wise SIC detection algorithm is thus proposed to further reduce the computational complexity.
Power controlling apparatus applied to biochip and operating method thereof
(2009-11-24)
Wu
;
Chung-Yu
;
Lin
;
Po-Kang
;
Lin
The invention discloses a power controlling apparatus for a biochip including M regions. Each region includes a plurality of cells respectively. The power controlling apparatus includes a pulse generating module, a combinational circuit, and M controlling modules. The pulse generating module generates a pulse. The combinational circuit receives the pulse and generates M controlling signals. Each controlling signal has a predetermined phase which is different from the phase of the other controlling signal. The M controlling modules are electrically connected to the combinational circuit. Each of the M controlling signals corresponds to and activates one of the M controlling modules to selectively power on one corresponding region of the M regions. The cells in the corresponding region which is powered have an action potential refractory time that is longer than the power-on interval of the corresponding region.
Selective area growth carbon nanotubes by metal imprint method
(2008-11-25)
Wu
;
YewChung Sermon
;
Chao
;
Chi Wei
;
Hou
Manufacturing methods of using a metal imprint technique for growing carbon nanotubes on selective areas and the structures formed thereof are provided. One of the manufacturing methods includes steps of forming a first substrate with tapered structures applied with a metal catalyst, imprinting a second substrate on the first substrate for being a growth substrate, and growing carbon nanotubes on the growth substrate. The other manufacturing method includes steps of forming a first substrate with tapered structures, imprinting the first substrate on a second substrate applied with a metal catalyst for forming a second growth substrate, and growing carbon nanotubes on the second grown substrate. And, the formed structures of the present invention include a substrate, plural carbon nanotubes, and plural imprinted vestiges.
Structure of high electron mobility transistor, a device comprising the structure and a method of producing the same
(2010-11-09)
Chang
;
Edward Yi.
;
Wu
;
Yun-Chi
;
Lin
Disclosed herein are a structure of a metal oxide semiconductor pseudomorphic high electron mobility transistor (MOS-PHEMT) suitable for use in a semiconductor device, such as a single-pole-double-throw (SPDT) switch of a monolithic microwave integrated circuit (MMIC); and a method of producing the same. The MOS-PHEMT structure is characterized in having a gate dielectric layer formed by atomic deposition from a gate dielectric selected from the group consisting of Al2O3, HfO2, La2O3, and ZrO2, and thereby rendering the semiconductor structure comprising the same, such as a high frequency switch device, to have less DC power loss, less insertion loss and better isolation.