Browsing by Author "Wu, Che-Chen"

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Epitaxial Germanium on SOI Substrate and Its Application of Fabricating High I-ON/I-OFF Ratio Ge FinFETs
(2013-06-01)
Chung, Cheng-Ting
;
Chen, Che-Wei
;
Lin, Jyun-Chih
;
Wu, Che-Chen
;
Chien, Chao-Hsin
Integrating germanium (Ge) thin film on silicon-on-insulator (SOI) substrate and fabricating Ge fin field-effect transistors (FinFETs) are demonstrated in this paper. Directly grown Ge film on a high-resistivity thin SOI substrate provides a good platform for fabricating advanced Ge devices. The SOI structure could effectively suppress junction leakage; therefore, high I-ON/I-OFF ratio (similar to 5 x 10(5), at V-D = 0.1 V) of the drain current is achieved. Tri-gate structure provides better short-channel control abilities for the Ge FinFETs, and the drain-induced barrier lowering and threshold voltage (V-TH) shift can be maintained at the level of similar to 110 mV/V and similar to 0.1 V, respectively, for Ge n-channel FinFET with L-channel = 120 nm and W-Fin = 40 nm. Multifin Ge FinFET with L-channel = 170 nm and W-Fin = 50 nm is also illustrated. Both N-and P-FinFETs possess high I-ON/I-OFF ratio over 104. Besides, the subthreshold swing could be reduced around 25% after forming gas annealing.
First Experimental Ge CMOS FinFETs Directly on SOI Substrate
(2012)
Chung, Cheng-Ting
;
Chen, Che-Wei
;
Lin, Jyun-Chih
;
Wu, Che-Chen
;
Chien, Chao-Hsin
High-performance Ge CMOS FinFETs directly on thin silicon on insulator (SOI) wafer are demonstrated. For the first time, NFET of L-channel = 120nm and Fin width=40nm with high I-on/I-off ratio (>10(5)), excellent drain induced barrier lowering (DIBL) (110mV/V) and subthreshold swing (S. S) (144mV/dec) has been shown. Both Ge n- and p-channel FinFETs with multi-fins have been achieved. Even the NFET of L-channel =90nm exhibits a pretty well on-off behavior after forming gas annealing.